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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
1. DESCRIPTION
The M37212M6-XXXSP/FP, M37212M4/M8-XXXSP are single-chip microcomputers designed with CMOS silicon gate technology. They have a OSD, I2C-BUS interface, and PWM, so it is useful for a channel selection system for TV. The feature of the M37212EFSP/FP are similar to those of the M37212M6-XXXSP/FP except that these chips have a built-in PROM which can be written electrically. The differences between the M37212M6-XXXSP/FP and M37212M4/M8-XXXSP are the ROM size and the RAM size as shown below. Accordingly, the following descriptions will be for M37212M6-XXXSP/FP unless otherwise noted.
qOSD function Display characters ................................... 24 characters ! 2 lines (It is possible to display 3lines or more by software) Kinds of characters ........................................................ 256 kinds Character display area .............................................. 12 ! 16 dots Kinds of character sizes ..................................................... 3 kinds Kinds of character colors .................................. 8 colors (R, G, B) Coloring unit ................... character, character background, raster Display position ............................................................................. Horizontal: 64 levels Vertical: 128 levels Attribute .............................................................................. border
2. FEATURES
of basic instructions ..................................................... 71 qMemory size ROM............... ......... 16K bytes (M37212M4-XXXSP) 24K bytes (M37212M6-XXXSP/FP) 32K bytes (M37212M8-XXXSP) 62K bytes (M37212EFSP/FP) RAM ......................... 320 bytes (M37212M4-XXXSP) 384 bytes (M37212M6-XXXSP/FP) 576 bytes (M37212M8-XXXSP) 1280 bytes (M37212EFSP/FP) (*ROM correction memory included) qThe minimum instruction execution time ......................................... 0.5 s (at 8 MHz oscillation frequency) qPower source voltage .................................................. 5 V 10 % qSubroutine nesting maximum 96 levels (M37212M4/M8-XXXSP, M37212M6-XXXSP/FP) maximum 128 levels (M37212EFSP/FP) qInterrupts ........................................................ 14 types, 14 vectors q8-bit timers ................................................................................... 4 qProgrammable I/O ports (Ports P0, P10-P14, P2, P30, P31, P40, P41) ............................. 25 qInput ports (Ports P15-P17, P32-P37, P42) ............................... 10 qOutput ports (Ports P52-P55, P60-P63) ....................................... 8 q12 V withstand ports .................................................................. 12 qLED drive ports ............................................................................ 4 qSerial I/O ............................................................. 8-bit ! 1 channel qMulti-master I2C-BUS interface ............................... 1 (2 systems) qA-D comparator (6-bit resolution) ................................. 8 channels qPWM output circuit .......................................... 14-bit ! 1, 8-bit ! 8 qPower dissipation .............................................................. 165 mW (at 8 MHz oscillation frequency, VCC=5.5V, at OSD display) qROM correction function ................................................. 2 vectors Note: Only M37212M8-XXXSP and M37212EFSP/FP have ROM correction function.
qNumber
3. APPLICATION
TV
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
TABLE OF CONTENTS
1. DESCRIPTION .......................................................................... 1 2. FEAUTURES ............................................................................. 1 3. APPLICATION ............................................................................ 1 4. PIN CONFIGURATION .............................................................. 3 5. FUNCTIONAL BLOCK DIAGRAM ............................................. 5 6. PERFORMANCE OVERVIEW ................................................... 6 7. PIN DESCRIPTION ................................................................... 8 8. FUNCTIONAL DESCRIPTION ................................................. 12 8.1 CENTRAL PROCESSING UNIT (CPU) .................... 12 8.2 MEMORY .................................................................. 13 8.3 INTERRUPTS ........................................................... 19 8.4 TIMERS ..................................................................... 24 8.5 SERIAL I/O ................................................................ 27 8.6 MULTI-MASTER I2C-BUS INTERFACE .................... 31 8.7 PWM OUTPUT CIRCUIT .......................................... 44 8.8 A-D COMPARATOR .................................................. 49 8.9 ROM CORRECTION FUNCTION ............................. 51 8.10 OSD FUNCTIONS ................................................... 52 8.10.1 Display Position ....................................... 56 8.10.2 Character Size ......................................... 60 8.10.3 Clock for OSD .......................................... 62 8.10.4 Memory for OSD ...................................... 63 8.10.5 Color Register .......................................... 66 8.10.6 Border ...................................................... 68 8.10.7 Multiline Display ....................................... 69 8.10.8 OSD Output Pin Control .......................... 70 8.10.9 Raster Coloring Function ......................... 71 8.11. SOFTWARE RUNAWAY DETECT FUNCTION ...... 72 8.12. RESET CIRCUIT .................................................... 73 8.13. CLOCK GENERATING CIRCUIT ........................... 74 8.14. DISPLAY OSCILLATION CIRCUIT ........................ 75 8.15. AUTO-CLEAR CIRCUIT ......................................... 75 8.16. ADDRESSING MODE ............................................ 75 8.17. MACHINE INSTRUCTIONS ................................... 75 9. PROGRAMMING NOTES ........................................................ 75 10. ABSOLUTE MAXIMUM RATINGS ......................................... 76 11. RECOMMENDED OPERATING CONDITIONS ..................... 76 12. ELECTRIC CHARACTERISTICS .......................................... 77 13. A-D COMPARISON CHARACTERISTICS ............................. 79 14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS ........... 79 15. PROM PROGRAMMING METHOD ....................................... 80 16. DATA REQUIRED FOR MASK ORDERS .............................. 81 17. MASK CONFIRMATION FORM ............................................. 82 18. MARK SPECIFICATION FORM ............................................. 91 19. ONE TIME PROM VERSIONS M37212EFSP/FP MARKING .... 93 20. APPENDIX ............................................................................. 94 21. PACKAGE OUTLINE ........................................................... 117
Rev. 1.0
2
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
4. PIN CONFIGURATION
HSYNC VSYNC P60/PWM0 P61/PWM1 P62/PWM2 P63/PWM3 P00/PWM4 P01/PWM5 P02/PWM6 P03/PWM7 P42/SIN/A-D5 P41/SCLK/A-D6 P40/SOUT(/IN)/A-D7 DA P35/INT2/A-D4 P34/INT1 P33/TIM3 P32/TIM2 P24 P25 P26 P27 CNVSS XIN XOUT VSS
1 2 3 4 5
52 51 50 49 48
P52/R P53/G P54/B P55/OUT1 P20 P21 P22 P23 P04 P05 P06 P07 P10/OUT2/A-D8 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/INT3/A-D1 P16/A-D2 P17/A-D3 P30 P31 RESET OSC1/P36 OSC2/P37 VCC
M37212M4/M6/M8-XXXSP, M37212EFSP
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
Outline 52P4B
Fig. 4.1 Pin Configuration 1 (Top View)
Rev. 1.0
3
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
P04 P05 P06 P07 P10/OUT2/A-D8 NC P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 NC
P15/INT3/A-D1 P16/A-D2 P17/A-D3
47 46 45
P22 P23
NC NC NC
NC
53
64
63
62
61
60
59
58
57
56
54
52
51
50
49
48
44
43
42
P21 NC P20 P55/OUT1 P54/B P53/G P52/R NC NC HSYNC VSYNC P60/PWM0 P61/PWM1 P62/PWM2 NC P63/PWM3
55
41
NC NC NC NC
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
20
40 39 38 37 36 35 34
P30 NC P31 RESET OSC1/P36 OSC2/P37 VCC NC NC VSS XOUT XIN CNVSS P27 NC NC
M37212M6-XXXFP, M37212EFFP
33 32 31 30 29 28 27 26 25 21 22 23
10
11
12
13
14
15
16
17
18
Outline 80P6N-A
Fig. 4.2 Pin Configuration 2 (Top View)
P40/SOUT(/IN)/A-D7 DA P35/INT2/A-D4 P34/INT1 P33/TIM3
NC NC NC NC P00/PWM4 P01/PWM5 P02/PWM6 P03/PWM7 NC P42/SIN/A-D5 P41/SCLK/A-D6
P32/TIM2 P24 P25 P26 NC NC NC NC
19
24
1
2
3
4
5
6
7
8
9
NC : Unconnected
Rev. 1.0
4
INT3
INT2
SDA
SCL
SIN SCLK SOUT(/IN)
PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
P0 (8)
INT1
OUT2
OUT1 B G R
4142 434410 9 8 7 14 1516 1718 3132
33 34353637383940
2221201945 464748
1112 13
6543
49 505152
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
MITSUBISHI MICROCOMPUTERS
I/O port P0
I/O ports P10-P14 Input ports P15-P17 I/O port P2
DA
Input port P42 I/O ports P30, P31 I/O ports P40, P41 Input ports P32-P35
Output ports P60-P63 Output ports P52-P55 Output for display
VSYNC HSYNC
Rev. 1.0
VCC VSS CNVSS
26 23 29 28 27
Clock input Clock output XIN XOUT ( ) Timing output
30
Reset input RESET
Input ports P36, P37 Clock input for display Clock output for display OSC1 OSC2
24
25
Clock generating circuit
TIM2 TIM3
Data bus
Fig. 5.1 Functional Block Diagram of M37212
Timer count source selection circuit
Program counter
5. FUNCTIONAL BLOCK DIAGRAM
RAM ROM PCL (8) Timer 2 T2 (8) Timer 3 T3 (8) Control signal Instruction decoder Instruction register (8) CRT circuit Timer 4 T4 (8)
Program counter
Timer 1 T1 (8)
PCH (8)
Address bus
8-bit arithmetic and logical unit Index register Y (8) Stack pointer S (8)
Accumulator A (8)
Processor status register PS (8)
Index register X (8)
A-D comparator
Multi-master I2C-BUS interface
14-bit PWM circuit
P3 (6)
SI/O(8)
P4 (3)
8-bit PWM circuit
P6 (4)
P5 (4)
P1 (8)
P2 (8)
21
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
5
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
6. PERFORMANCE OVERVIEW
Table 6.1 Performance Overview Parameter Number of basic instructions Number of basic instructions Instruction execution time Memory size ROM M37212M4-XXXSP M37212M8-XXXSP M37212EFSP/FP RAM M37212M4-XXXSP M37212M8-XXXSP M37212EFSP/FP OSD ROM OSD RAM Input/Output ports P0 P10-P14 I/O I/O 71 0.5 s (the minimum instruction execution time, at 8 MHz oscillation fre quency) 8 MHz (maximum) 16K bytes 32K bytes 62K bytes 320 bytes 576 bytes (ROM correction memory included) 1280 bytes (ROM correction memory included) 8 K bytes 96 bytes 8-bit ! 1 (N-channel open-drain output structure, can be used as PWM output pins) 5-bit ! 1 (CMOS input/output output structure, however, N-channel opendrain output structure, when P11-P14 are used as multi-master I2C-BUS interface, can be used as OSD output, A-D input, multi-master I2C-BUS interface) 3-bit ! 1 (can be used as INT input pin, A-D input pins) 8-bit ! 1 (CMOS input/output structure) 2-bit ! 1 (CMOS input/output structure) 6-bit ! 1 (can be used as external clock input pins, INT input pins, OSD display clock I/O pins, A-D input pins) 2-bit ! 1 (N-channel open-drain output structure, can be used as serial I/O pins, A-D input pins) 1-bit ! 1(can be used as serial input pin, A-D input pin) 4-bit ! 1 (CMOS output structure, can be used as OSD output pins) 4-bit ! 1 (N-channel open-drain output structure, can be used as PWM output pins) 8-bit ! 1 1 (2 systems) 8 channels (6-bit resolution) 14-bit ! 1, 8-bit ! 8 8-bit timer ! 4 96 levels (maximum) <14 sources> INT external interrupt ! 3, Internal timer interrupt ! 4, Serial I/O interrupt ! 1, OSD interrupt ! 1, Multi-master I2C-BUS interface interrupt ! 1, f(XIN)/4096 interrupt ! 1, VSYNC interrupt ! 1, BRK interrupt ! 1, Reset ! 1 2 built-in circuits (externally connected a ceramic resonator or a quartzcrystal oscillator) M37212M6-XXXSP/FP 24K bytes Functions
M37212M6-XXXSP/FP 384 bytes
P15-P17 P20-P27 P30, P31 P32-P37 P40, P41 P42 P52-P55 P60-P63 Serial I/O Multi-master I2C-BUS interface A-D comparator PWM output circuit Timers Subroutine nesting Interrupt
Input I/O I/O Input I/O Input Output Output
Clock generating circuit
Rev. 1.0
6
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Table 6.2 Performance Overview (continued) Parameter OSD display function Number of display characters Dot structure Kinds of characters Kinds of character sizes Character font coloring Display position Power source voltage Power dissipation OSD ON OSD OFF In stop mode Operating temperature range Device structure Package M37212M4/M6/M8-XXXSP, M37212EFSP M37212M6-XXXFP, M37212EFSP 24 characters ! 2 lines 12 ! 16 dots 254 kinds 3 kinds 1 screen: 8 kinds (per character unit) Horizontal: 64 levels, Vertical: 128 levels 5 V 10 % 165 mW typ. (at oscillation frequency f(XIN) = 8 MHz, fOSC = 8 MHz) 110 mW typ. (at oscillation frequency f(XIN) = 8 MHz) 1.65 mW (maximum) -10 C to 70 C CMOS silicon gate process 52-pin plastic molded SDIP 80-pin plastic molded QFP Functions
Rev. 1.0
7
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
7. PIN DESCRIPTION
Table 7.1 Pin Description Pin VCC, VSS. CNVSS
______
Name Power source CNVSS Reset input
Input/ Output
Functions Apply voltage of 5 V 10 % to (typical) VCC, and 0 V to VSS. This is connected to VSS.
RESET
Input
To enter the reset state, the reset input pin must be kept at a "L" for 2 s or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this "L" condition should be maintained for the required time. This chip has an internal clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT. If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. Port P0 is an 8-bit I/O port with direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is N-channel open-drain output. (See note) Pins P00-P03 are also used as PWM output pins PWM4-PWM7 respectively. The output structure is N-channel open-drain output. Port P10-P14 are a 5-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Pins P10 is also used as OSD output pin OUT2. The output structure is CMOS output. Pins P11-P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I2C-BUS interface is used. The output structure is N-channel open-drain output. P10 pin is also used as analog input pin A-D8. Port P15-P17 are a 3-bit input port and has basically the same functions as port P0. Pins P15-P17 are also used as analog input pins A-D1 to A-D3 respectively. P15 pin is also used as INT external interrupt input pin INT3. Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. (See note) Ports P30, P31 are a 2-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. Ports P32-P37 are a 6-bit input port and has basically the same functions as port P0. Pins P32, P33 are also used as external clock input pins TIM2, TIM3 respectively. Pins P34, P35 are also used as INT external interrupt input pins INT1, INT2 respectively. P35 pin is also used as analog input pin A-D4. P36 pin is also used as OSD display clock input pin OSC1. P37 pin is also used as OSD display clock output pin OSC2. The output structure is CMOS output.
XIN XOUT
Clock input Clock output
Input Output I/O
P00/PWM4- I/O port P0 P03/PWM7, P04-P07 PWM output P10/OUT2/ I/O port P1 A-D8, P11/SCL1, OSD output P12/SCL2, Multi-master P13/SDA1, I2C-BUS interface P14/SDA2, Analog input P15/INT3/ A-D1, P16/A-D2, P17/A-D3 P20-P27 P30, P31 P32/TIM2, P33/TIM3, P34/INT1, P35/INT2/ A-D4, Input port P1 Analog input External interrupt input I/O port P2 I/O port P3 Input port P3 External clock input External interrupt input Analog input
Output I/O Output I/O Input Input Input Input I/O I/O Input Input Input Input Input Output
P36/OSC1, Clock input for P37/OSC2 OSD display Clock output for OSD display
Rev. 1.0
8
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Table 7.2 Pin Description (continued) Pin Name Input/ Output I/O I/O I/O Input Input Input Input Output Output Output Output Input Input Output Functions Ports P40, P41 are a 2-bit I/O port and has basically the same functions as port P0. The output structure is N-channel open-drain output. Pin P40 is also used as serial I/O data input/output pin SOUT(/IN). The output structure is Nchannel open-drain output. Pin P41 is also used as serial I/O synchronizing clock input/output pin SCLK. The output structure is N-channel open-drain output. Pin P40, P41 are also used as analog input pins A-D7, A-D6 respectively. Port P42 is a 1-bit input port and has basically the same functions as port P0. Pin P42 is also used as serial I/O data input pin SIN. Pin P42 is also used as analog input pin A-D5. Ports P52-P55 are a 4-bit output port and has basically the same functions as port P0. The output structure is CMOS output. Pins P52-P55 are also used as OSD output pins R, G, B, OUT1 respectively. The output structure is CMOS output. Ports P60-P63 are a 4-bit I/O port and has basically the same functions as port P0. The output structure is N-channel open-drain output. Pins P60-P63 are also used as PWM output pins PWM0-PWM3 respectively. The output structure is N-channel open-drain output. This is a horizontal synchronizing signal input for OSD. This is a vertical synchronizing signal input for OSD. This is a 14-bit PWM output pin.
P40/SOUT(/IN)/ I/O port P4 A-D7, P41/SCLK/ A-D6, Serial I/O data input/output Serial I/O synchronizing clock input/output Analog input pin P42/SIN/ A-D5, Input port P4 Serial I/O data input Analog input P52/R, P53/G, P54/B, P55/OUT1 Output port P5 OSD output
P60PWM0- Output port P6 P63/PWM3 PWM output HSYNC VSYNC DA HSYNC input VSYNC input DA output
Note : Port Pi (i = 0 to 3) has the port Pi direction register which can be used to program each bit as an input ("0") or an output ("1"). The pins programmed as "1" in the direction register are output pins. When pins are programmed as "0," they are input pins. When pins are programmed as output pins, the output data are written into the port latch and then output. When data is read from the output pins, the output pin level is not read but the data of the port latch is read. This allows a previously-output value to be read correctly even if the output "L" voltage has risen, for example, because a light emitting diode was directly driven. The input pins are in the floating state, so the values of the pins can be read. When data is written into the input pin, it is written only into the port latch, while the pin remains in the floating state.
Rev. 1.0
9
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Port P0
N-channel open-drain output
Direction register
Port P0
Data bus Port latch
Note : Each port is also used as follows : P00-P03 : PWM4-PWM7
Ports P10, P2, P30, P31 Direction register
CMOS output Ports P10, P2, P30, P31 Note : Port P10 is also used as OUT2/ A-D8.
Data bus
Port latch
Ports P40, P41 Direction register
SIN, SCLK
N-channel open-drain output Ports P40, P41
Data bus
Port latch
Note : Each port is also used as follows : P40 : SOUT(/IN)/A-D7 P41 : SCLK/A-D6
Ports P11-P14
BSEL0 BSEL1 Direction register
SCL1, SCL2, SDA1, SDA2
N-channel open-drain output CMOS output Ports P11-P14 Notes 1: Each port is also used as follows : P11 : SCL1 P12 : SCL2 P13 : SDA1 P14 : SDA2 2: The output structure of ports P11- P14 is N-channel open-drain output when using as multi-master I2CBUS interface (it is the same with ports P40 and P41).
Data bus I2C-BUS clock I2C-BUS data
Port latch
Fig. 7.1 I/O Pin Block Diagram (1)
Rev. 1.0
10
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Ports P16, P17
Data bus
Ports P16, P17 Note : Each port is also used as follows : P16 : A-D2 P17 : A-D3
Ports P15, P32-P37, P42
Schmidt input
TIM2, TIM3, INT1, INT2, SIN, INT3 Data bus
Ports P15, P32-P37, P42 Note : Each port is also used as follows : P15 : INT3/A-D1 P32 : TIM2 P33 : TIM3 P34 : INT1 P35 : INT2/A-D4 P36 : OSC1 P37 : OSC2 P42 : SIN/A-D5 N-chanel open drain output Ports P60-P63
Ports P60-P63
Data bus
Port latch
Note : Each port is also used as follows : P60-P63 : PWM0-PWM3
D-A, R, G, B, OUT1 , OUT2
CMOS output
Internal circuit
Ports D-A, R, G, B, OUT1, OUT2 Note : Each pin is also used as follows : R : P52 G : P53 B : P54 OUT1 : P55 OUT2 : P10/A-D8
HSYNC, VSYNC
Schmidt input
Internal circuit
Ports HSYNC, VSYNC
Fig. 7.2 I/O Pin Block Diagram (2)
Rev. 1.0
11
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8. FUNCTIONAL DESCRIPTION 8.1 CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the SERIES 740 User's Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instructions can be used.
8.1.1 CPU Mode Register
The CPU mode register contains the stack page selection bit and internal system clock selection bit. The CPU mode register is allocated at address 00FB16.
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 11111 00 CPU mode register (CM) [Address 00FB16] B Name Functions
After reset R W
Indeterminate
0, 1 Fix these bits to "0." 2 Stack page selection bit (CM2) (See note) 0: 0 page 1: 1 page
RW RW RW
1
Indeterminate
3 to 7 Fix these bits to "1." Note: This bit is set to "1" after the reset release.
Fig. 8.1.1 CPU Mode Register
Rev. 1.0
12
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.2 MEMORY 8.2.1 Special Function Register (SFR) Area
The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.
8.2.7 Zero Page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
8.2.2 RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
8.2.3 ROM
ROM is used for storing user programs as well as the interrupt vector area.
8.2.8 Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
8.2.4 OSD RAM
RAM for display is used for specifying the character codes and colors to display.
8.2.9 ROM Correction Memory (RAM) 8.2.5 OSD ROM
ROM for display is used for storing character data. This is used as the program area for ROM correction.
Note: Only M37212M8-XXXSP and M37212EFSP/FP have ROM correction memory.
8.2.6 Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
s M37212M4/M8-XXXSP, M37212M6-XXXSP/FP
000016 M37212M6XXXSP/FP RAM (384 bytes) M37212M4XXXSP RAM (320 bytes) 00BF16 00C016 00FF16 010016 017F16 01BF16 Zero page SFR area OSD ROM (8K bytes) 11FFF16 1000016
Not used
Not used OSD RAM (96 bytes) (See note) 060016 06B716 Not used
M37212M6XXXSP/FP ROM (24K bytes)
A00016 C00016
M37212M4XXXSP ROM (16K bytes) FF0016 FFDE16 FFFF16
Interrupt vector area
Special page 1FFFF16 Note: Refer to Table 8.10.3 OSD RAM.
Fig. 8.2.1 Memory Map (M37212M4/M8-XXXSP, M37212M6-XXXSP/FP)
Rev. 1.0
13
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
s M37212M8-XXXSP, M37212EFSP/FP
000016 00BF16 00C016 00FF16 010016 Zero page SFR area OSD ROM (8K bytes) 11FFF16 1000016
M37212EFSP RAM (1280 bytes)
M37212M8XXXSP RAM (576 bytes)
01FF16 021716 021B16
Not used 2 page register Not used
02C016 02E016 033F16 05FF16 060016
ROM correction function Vector 1: address 02C016 Vector 2: address 02E016
Not used
OSD RAM (96 bytes) (See note) M37212EFSP ROM (62K bytes)
06B716 Not used 080016 800016
M37212M8XXXSP ROM (32K bytes) FF0016 FFDE16 FFFF16
Interrupt vector area
Special page 1FFFF16 Note: Refer to Table 8.10.3 OSD RAM
Fig. 8.2.2 Memory Map (M37212M8-XXXSP, M37212EFSP/FP)
Rev. 1.0
14
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
s SFR area (addresses C016 to DF16)
Bit allocation :
Name
State immediately after reset 0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
Function bit
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Register
Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) Port P4 (P4) Port P4 direction register (D4) Port P5 (P5) Port P5 direction register (D5) Port P6 (P6) DA-H register (DA-H) DA-L register (DA-L) PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN) I2C I2 C data shift register (S0)
D7 D6 D5 PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 P N4 P N3 P N2 P N1 P N0 D4 D3 D2 D1 D0
P55 P55 SEL P54 P53 P52 P31D P30D P41 P40 P41D P40D
Bit allocation
b7
State immediately after reset
b0 b7 b0
0 0 0
0 0 0
0 0 ?
P54 P53 P52 SEL SEL SEL P63 P62
0 1
0 1 0 0 ?
P61 P60
1
1
address register (S0D) I2C status register (S1)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW MST TRX BB PIN AL AAS AD0 LRB
0
0
0
I2C control register (S1D) I2C clock control register (S2) Serial I/O mode register (SM) Serial I/O register (SIO)
BSEL1 BSEL0 10BIT ALS ESO BC2 BC1 BC0 SAD KF ACK ACT MAST CCR4 CCR3 CCR2 CCR1 CCR0 BI ODE
SM6 SM5
0
SM3 SM2 SM1 SM0
? 0016 ? 0016 ? 0016 ? 0016 00 00 ?? 0016 0F16 0F16 ? ?? ? ? ? ? ? 0016 0016 ? 0016 10 0016 0016 0016 ? ? ?
? ? ?
? ? 0
? ? 0
?
?
?
0
0
?
Fig. 8.2.3 Memory Map of Special Function Register (SFR) (1)
Rev. 1.0
15
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
s SFR area (addresses E016 to FF16)
Bit allocation :
Name
State immediately after reset 0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
Function bit
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Register
b7 Horizontal position register (HR) Vertical position register 1 (CV1) Vertical position register 2 (CV2) Character size register (CS) Border selection register (MD) Color register 0 (CO0) Color register 1 (CO1) Color register 2 (CO2) Color register 3 (CO3) CRT control register (CC) CRT port control register (CRTP)
Bit allocation
HR5 HR4 HR3 HR2 HR1 HR0 CV16 CV15 CV14 CV13 CV12 CV11 CV10 CV26 CV25 CV24 CV23 CV22 CV21 CV20
State immediately after reset
b0 b7 b0
0 0 0 0
? ? 0 0
? ? 0 0
CS21 CS20 CS11 CS10 MD20 CO07 CO06 CO05 CO04 CO03 CO02 CO01 CO17 CO16 CO15 CO14 CO13 CO12 CO11 CO27 CO26 CO25 CO24 CO23 CO22 CO21 CO37 CO36 CO35 CO34 CO33 CO32 CO31 MD10
CC7
CC2 CC1 CC0
OP7 OP6 OP5 OUT1 OUT2 R/G/B VSYC HSYC
CRT clock selection register (CK) 0 A-D mode register (ADM) A-D control register (ADC) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer 12 mode register (T12M) Timer 34 mode register (T34M) PWM5 register (PWM5) PWM6 register (PWM6) PWM7 register (PWM7) Interrupt input polarity register (RE) 0
0
0
0
ADM4
0
0
CK1 CK0
ADM2 ADM1 ADM0
0
0
0
ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
0
T12M4 T12M3 T12M2 T12M1 T12M0
T34M5 T34M4 T34M3 T34M2 T34M1 T34M0
RE5 RE4 RE3
0
CM2
1 CPU mode register (CM) Interrupt request register 1 (IREQ1) IT3R
Interrupt request register 2 (IREQ2) 0 Interrupt control register 1 (ICON1) IT3E Interrupt control register 2 (ICON2)
1
1
1
MSR CK 0
1
0
0
IICR VSCR OSDR TM4R TM3R TM2R TM1R
S1R IT2R IT1R
IICE VSCE OSDE TM4E TM3E TM2E TM1E
0
0
MSE
0
S1E IT2E IT1E
?
0
0
0016 ?? ?? 0016 0? 00 0016 0016 0016 0016 0016 0016 0016 0016 ?0 0016 FF16 0716 FF16 0716 0016 0016 ? ? ? 0016 ? FC16 0016 0016 0016 00
? ? ? ?
? ? ? 0
? ? ? ?
0
0
0
0
0
0
Fig. 8.2.4 Memory Map of Special Function Register (SFR) (2)
Rev. 1.0
16
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
s 2 page register area (addresses 21716 to 21B16)
:
Name
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
Function bit
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address 21716 21816 21916 21A16 21B16 Register
ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR)
Bit allocation
b7
State immediately after reset
b0 b7 b0
0
0
RCR1RCR0
0016 0016 0016 0016 0016
Note: Only M37212M8-XXXSP and M37212EFSP/FP have 2 page register.
Fig. 8.2.5 Memory Map of 2 Page Register Area
Rev. 1.0
17
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
:
Name
0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
Function bit
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Register
b7 Processor status register (PS) Program counter (PCH) Program counter (PCL)
Bit allocation N V T B D I Z C
State immediately after reset
b0 b7 b0
?????1?? Contents of address FFFF16 Contents of address FFFE16
Fig. 8.2.6 Internal State of Processor Status Register and Program Counter at Reset
Rev. 1.0
18
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.3 INTERRUPTS
Interrupts can be caused by 14 different sources consisting of 4 external, 8 internal, 1 software, and reset. Interrupts are vectored interrupts with priorities as shown in Table 8.3.1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, x The contents of the program counter and processor status register are automatically stored into the stack. The interrupt disable flag I is set to "1" and the corresponding interrupt request bit is set to "0." The jump destination address stored in the vector address enters the program counter. Other interrupts are disabled when the interrupt disable flag is set to "1." All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in interrupt request registers 1 and 2 and the interrupt enable bits are in interrupt control registers 1 and 2. Figures 8.3.2 to 8.3.6 show the interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is "1," interrupt request bit is "1," and the interrupt disable flag is "0." The interrupt request bit can be set to "0" by a program, but not set to "1." The interrupt enable bit can be set to "0" and "1" by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 8.3.1 shows interrupt control.
8.3.1 Interrupt Causes (1) VSYNC, OSD interrupts
The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The OSD interrupt occurs after character block display to the CRT is completed.
(2) INT1 to INT3 external interrupts
The INT1 to INT3 interrupts are external interrupt inputs, the system detects that the level of a pin changes from LOW to HIGH or from HIGH to LOW, and generates an interrupt request. The input active edge can be selected by bits 3 to 5 of the interrupt input polarity register (address 00F916) : when this bit is "0," a change from LOW to HIGH is detected; when it is "1," a change from HIGH to LOW is detected. Note that both bits are cleared to "0" at reset.
(3) Timers 1 to 4 interrupts
An interrupt is generated by an overflow of timers 1 to 4.
Table 8.3.1 Interrupt Vector Addresses and Priority Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Interrupt Source Reset OSD interrupt INT2 external interrupt INT1 external interrupt Timer 4 interrupt f(XIN)/4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt Serial I/O interrupt Multi-master I2C-BUS interface interrupt INT3 external interrupt BRK instruction interrupt Vector Addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF816 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE916, FFE816 FFE716, FFE616 FFE516, FFE416 FFDF16, FFDE16 Remarks Non-maskable Active edge selectable Active edge selectable
Active edge selectable Non-maskable
Rev. 1.0
19
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
(4) Serial I/O interrupt
This is an interrupt request from the clock synchronous serial I/O function.
(5) f(XIN)/4096 interrupt
The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of PWM output control register 1 to "0."
Interrupt request bit Interrupt enable bit
(6) Multi-master I2C-BUS interface interrupt
This is an interrupt request related to the multi-master I2C-BUS interface.
Interrupt disable flag I
BRK instruction Reset
Interrupt request
(7) BRK instruction interrupt
This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable). Fig. 8.3.1 Interrupt Control
Rev. 1.0
20
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC16] B Name 0 Timer 1 interrupt request bit (TM1R) 1 2 3 4 5 6 7 Functions After reset 0 0 : No interrupt request issued 1 : Interrupt request issued Timer 2 interrupt 0 0 : No interrupt request issued request bit (TM2R) 1 : Interrupt request issued 0 Timer 3 interrupt 0 : No interrupt request issued request bit (TM3R) 1 : Interrupt request issued 0 Timer 4 interrupt 0 : No interrupt request issued request bit (TM4R) 1 : Interrupt request issued OSD interrupt request 0 : No interrupt request issued 0 1 : Interrupt request issued bit (OSDR) VSYNC interrupt 0 0 : No interrupt request issued request bit (VSCR) 1 : Interrupt request issued 0 Multi-master I2C-BUS interface 0 : No interrupt request issued interrupt request bit (IICR) 1 : Interrupt request issued 0 0 : No interrupt request issued INT3 external interrupt request bit (IT3R) 1 : Interrupt request issued RW RV RV RV RV RV RV RV RV
V: "0" can be set by software, but "1" cannot be set.
Fig. 8.3.2 Interrupt Request Register 1
Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD16] B Name 0 INT1 external interrupt
request bit (IT1R)
Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued
After reset R W 0 0 0 0 0 0 0 RV RV RV R-- RV R-- RW
1 2
INT2 external interrupt request bit (IT2R)
0 : No interrupt request issued 1 : Interrupt request issued 3 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." 4 f(XIN)/4096 interrupt 0 : No interrupt request issued request bit (MSR) 1 : Interrupt request issued 5, 6 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 7 Fix this bit to "0." V: "0" can be set by software, but "1" cannot be set.
Serial I/O interrupt request bit (S1R)
Fig. 8.3.3 Interrupt Request Register 2
Rev. 1.0
21
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW
0 Timer 1 interrupt enable bit (TM1E) 1 Timer 2 interrupt enable bit (TM2E) 2 Timer 3 interrupt enable bit (TM3E) 3 Timer 4 interrupt enable bit (TM4E) 4 OSD interrupt enable bit (OSDE) 5 VSYNC interrupt enable bit (VSCE)
6 Multi-master I2C-BUS interface 0 : Interrupt disabled interrupt enable bit (IICE) 1 : Interrupt enabled 7 INT3 external interrupt enable bit (IT3E) 0 : Interrupt disabled 1 : Interrupt enabled
Fig. 8.3.4 Interrupt Control Register 1
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 00 0 Interrupt control register 2 (ICON2) [Address 00FF16] B Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset 0 0 0 0 0 : Interrupt disabled 1 : Interrupt enabled 0 0
indeterminate
RW RW RW RW RW RW RW R-
0 INT1 external interrupt enable bit (IT1E) 1 INT2 external interrupt enable bit (IT2E) 2 Serial I/O interrupt enable bit (S1E) 3 Fix this bit to "0." 4 f(XIN)/4096 interrupt enable bit (MSE) 5, 6 Fix these bits to "0." 7
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "indeterminate."
Fig. 8.3.5 Interrupt Control Register 2
Rev. 1.0
22
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Interrupt input polarity register(RE) [Address 00F916]
B
Name
Functions
After reset 0 0
RW R-- RW RW RW RW R-- RW
0, 1 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 2 3 4 5 6 7 Fix this bit to "0." INT1 polarity switch bit (RE3) INT2 polarity switch bit ( E 4) R INT3 polarity switch bit ( E 5) R 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity
0 0 0 0 0
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." Fix this bit to "0."
Fig. 8.3.6 Interrupt Input Polarity Register
Rev. 1.0
23
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.4 TIMERS
This microcomputer has 4 timers: timers 1 to 4. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 8.4.3. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4), the value is also set to a timer, simultaneously. The count value is decremented by 1. The timer interrupt request bit is set to "1" by a timer overflow at the next count pulse, after the count value reaches "0016."
8.4.1 Timer 1
Timer 1 can select one of the following count sources: * f(XIN)/16 * f(XIN)/4096 The count source of timer 1 is selected by setting bit 0 of timer 12 mode register 1 (address 00F416). Timer interrupt request occurs at timer 1 overflow.
At reset, timers 3 and 4 are connected by hardware and "FF16" is automatically set in timer 3; "0716" in timer 4. The f(XIN)/16 is selected as the timer 3 count source. The internal reset is released by timer 4 overflow in this state and the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and "FF16" is automatically set in timer 3; "0716" in timer 4. However, the f(XIN)/16 is not selected as the timer 3 count source. So set both bit 0 of timer 34 mode register (address 00F516) and bit 6 at address 00C716 to "0" before execution of the STP instruction (f(XIN)/16 is selected as the timer 3 count source). The internal STP state is released by timer 4 overflow in this state and the internal clock is connected. As a result of the above procedure, the program can start under a stable clock. The timer-related registers is shown in Figures 8.4.1 and 8.4.2.
8.4.2 Timer 2
Timer 2 can select one of the following count sources: * f(XIN)/16 * Timer 1 overflow signal * External clock from the TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of timer 12 mode register (address 00F416). When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow.
8.4.3 Timer 3
Timer 3 can select one of the following count sources: * f(XIN)/16 * External clock from the HSYNC pin * External clock from the TIM3 pin The count source of timer 3 is selected by setting bits 5 and 0 of timer 34 mode register (address 00F516). Timer 3 interrupt request occurs at timer 3 overflow.
8.4.4 Timer 4
Timer 4 can select one of the following count sources: * f(XIN)/16 * f(XIN)/2 * Timer 3 overflow signal The count source of timer 3 is selected by setting bits 1 and 4 of timer 34 mode register (address 00F516). When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow.
Rev. 1.0
24
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Timer 12 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 0 Timer mode register (T12M) [Address 00F416] B 0 1 Name Functions After reset R W 0 0 0 0 0 RW RW RW RW RW
Timer 1 count source 0: f(XIN)/16 selection bit 1 (T12M0) 1: f(XIN)/4096 Timer 2 count source selection bit (T12M1) 0: Interrupt clock source 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 1: Timer 1 overflow
2 Timer 1 count stop bit (T12M2) 3 Timer 2 count stop bit (T12M3) 4 Timer 2 internal count source selection bit 2 (T12M4) 5 Fix this bit to "0."
0 0
RW R--
6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
Fig. 8.4.1 Timer 12 Mode Register
Timer 34 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 34 mode register (T34M) [Address 00F516] B Name 0 Timer 3 count source selection bit (T34M0) 1 Timer 4 internal interrupt count source selection bit (T34M1) Functions 0 : f(XIN)/16 1 : External clock source 0 : Timer 3 overflow signal 1 : f(XIN)/16 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Internal clock source 1: f(XIN)/2 After reset R W 0 RW 0 RW
2 Timer 3 count stop bit (T34M2) 3 Timer 4 count stop bit (T34M3) 4 Timer 4 count source selection bit (T34M4) 5
0 0 0 0
RW RW RW RW
Timer 3 external count 0: TIM3 pin input source selection bit 1: HSYNC pin input (T34M5)
6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
0
R--
Fig. 8.4.2 Timer 34 Mode Register
Rev. 1.0
25
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Data bus
8
1/4096
Timer 1 latch (8) 8
XIN
1/2
1/8 T12M0 T12M2
Timer 1 (8) 8 T12M4 8
Timer 1 interrupt request
Timer 2 latch (8) 8 TIM2 T12M1 T12M3 8 Timer 2 (8) Timer 2 interrupt request
HSYNC
8
FF16
Reset STP instruction
TIM3
T34M5
Timer 3 latch (8)
8
Timer 3 (8) T34M0 T34M2 8 Timer 3 interrupt request
Selection gate : Connected to black colored side at reset T34M1 T12M : Timer 12 mode register T34M : Timer 34 mode register Timer 4 latch (8) 8 Timer 4 (8) T34M4 T34M3
8 0716
Timer 4 interrupt request 8
Notes 1: "H" pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal. 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used.
Fig. 8.4.3 Timer Block Diagram
Rev. 1.0
26
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.5 SERIAL I/O
This microcomputer has a built-in serial I/O which can either transmit or receive 8-bit data serially in the clock synchronous mode. The serial I/O block diagram is shown in Figure 8.5.1. The synchronous clock I/O pin (SCLK), data output pin (SOUT), and data input pin (SIN) also functions as port P4. Bit 3 of the serial I/O mode register (address 00DC16) selects whether the synchronous clock is supplied internally or externally (from the SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) or f(XCIN) is divided by 4, 16, 32, or 64. To use SIN pin for serial I/O, set the corresponding bit of the port P2 direction register (address 00C516) to "0."
The operation of the serial I/O is described below. The operation of the serial I/O differs depending on the clock source; external clock or internal clock.
Data bus XIN 1/2 1/2 Frequency divider
1/4 1/8 1/16
SM2
S
SM1 SM0
Synchronization circuit
Selection gate : Connected to black colored side at reset. SM : Serial I/O mode register
P41 latch SCLK SM3 P40 latch SOUT(/IN) SIN SM6 SM5 : LSB SM3 MSB (See note) Serial I/O shift register (8) (Address 00DD16) 8 Serial I/O counter (8) Serial I/O interrupt request
Note : When the data is set in the serial I/O register (address 00DD 16), the register functions as the serial I/O shift register.
Fig. 8.5.1 Serial I/O Block Diagram
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Internal clock : The serial I/O counter is set to "7" during the write cycle into the serial I/O register (address 00DD16), and the transfer clock goes HIGH forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes "0" and the transfer clock stops at HIGH. At this time the interrupt request bit is set to "1."
External clock : The an external clock is selected as the clock source, the interrupt request is set to "1" after the transfer clock has been counted 8 counts. However, transfer operation does not stop, so the clock should be controlled externally. Use the external clock of 1 MHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 8.5.2. When using an external clock for transfer, the external clock must be held at HIGH for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching.
Notes 1: On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing instructions, such as SEB and CLB. 2: When an external clock is used as the synchronous clock, write transmit data to the serial I/O register when the transfer clock input level is HIGH.
Synchronous clock
Transfer clock Serial I/O register write signal (See note) Serial I/O output SOUT Serial I/O input SIN D0 D1 D2 D3 D4 D5 D6 D7
Interrupt request bit is set to "1" Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed.
Fig. 8.5.2 Serial I/O Timing (for LSB first)
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Serial I/O Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 0 Serial I/O mode register (SM) [Address 00DC16] B Name
b1 b0
Functions 0 0: f(XIN)/4 0 1: f(XIN)/16 1 0: f(XIN)/32 1 1: f(XIN)/64 0: External clock 1: Internal clock 0: P40, P41 1: SOUT(/IN), SCLK
0, 1 Internal synchronous clock selection bits (SM0, SM1)
After reset R W 0 RW
2 3
Synchronous clock selection bit (SM2) Serial I/O port selection bit (SM3)
0 0
RW RW
4 Fix this bit to "0." 5 6 7 Transfer direction selection bit (SM5) Serial input pin selection bit (SM6) 0: LSB first 1: MSB first 0: Input signal from SIN pin. 1: Input signal from SOUT pin.
0 0 0 0
RW RW RW R--
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
Fig. 8.5.3 Serial I/O Mode Register
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.5.1 Serial I/O Common Transmission/Reception mode
By writing "1" to bit 6 of the serial I/O mode register, signals SIN and SOUT are switched internally to be able to transmit or receive the serial data. Figure 8.5.4 shows signals on serial I/O common transmission/reception mode.
Note: When receiving the serial data after writing "FF16" to the serial I/O register.
SCLK
Clock
SOUT(/IN) "1" Serial I/O shift register (8) SIN "0" SM6
SM : Serial I/O mode register
Fig. 8.5.4 Signals on Serial I/O Common Transmission/Reception Mode
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.6 MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 8.6.1 shows a block diagram of the multi-master I2C-BUS interface and Table 8.6.1 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits.
Table 8.6.1 Multi-master I2C-BUS Interface Functions Item Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at = 4 MHz)
Format
Communication mode
SCL clock frequency
: System clock = f(XIN)/2
Note : We are not responsible for any third party's infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 00DA16) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2).
b7
I2C address register (S0D) b0
Interrupt generating circuit Interrupt request signal (IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Address comparator Serial data
(SDA)
Noise elimination circuit
Data control circuit
b7
I C data shift register S0
2
b0 b7
MST TRX BB PIN
b0
AL AAS AD0 LRB
AL circuit
Internal data bus
I C status register (S1)
2
BB circuit
Serial clock
(SCL)
Noise elimination circuit
Clock control circuit
b7
ACK
b0
ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE BIT
b7
BSEL1 BSEL0 10BIT SAD ALS
b0
ESO BC2 BC1 BC0
I2C clock control register (S2) Clock division
I2C control register (S1D) System clock () Bit counter
Fig. 8.6.1 Block Diagram of Multi-master I2C-BUS Interface
Rev. 1.0
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8.6.1 I2C Data Shift Register
The I2C data shift register (S0 : address 00D716) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ESO bit of the I2C control register (address 00DA16) is "1." The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register (address 00D916) are "1," the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value.
Note: To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
I2C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C data shift register (S0) [Address 00D716] B 0 to 7 Name Functions After reset Indeterminate RW RW
D0 to D7 This is an 8-bit shift register to store receive data and write transmit data.
Note: To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
Fig. 8.6.2 Data Shift Register
Rev. 1.0
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8.6.2 I2C Address Register
The I2C address register (address 00D816) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition are detected.
(1) Bit 0: read/write bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2C address register. The RBW bit is cleared to "0" automatically when the stop condition is detected.
(2) Bits 1 to 7: slave address (SAD0-SAD6)
These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits.
I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00D816] B
0
Name
Read/write bit (RBW)
Functions
The last significant bit of address data is compared. 0: Wait the first byte of slave address after START condition (read state) 1: Wait the first byte of slave address after RESTART condition (write state) The address data is compared.
After reset R W
0
R--
1 to 7
Slave address (SAD0 to SAD6)
0
RW
Fig. 8.6.3 I2C Address Register
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.6.3 I2C Clock Control Register
The I2C clock control register (address 00DB16) is used to set ACK control, SCL mode and SCL frequency.
(4) Bit 7: ACK clock bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to "0," the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to "1," the ACK clock mode is set and the master generates an ACK clock upon completion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data receiving device.
Note: Do not write data into the I2C clock control register during transmission. If data is written during transmission, the I2C clock generator is reset, so that data cannot be transmitted normally.
(1) Bits 0 to 4: SCL frequency control bits (CCR0-CCR4)
These bits control the SCL frequency.
(2) Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to "0," the standard clock mode is set. When the bit is set to "1," the high-speed clock mode is set.
(3) Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clockV is generated. When this bit is set to "0," the ACK return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to "1," the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = "0," the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made HIGH (ACK is not returned). VACK clock: Clock for acknowledgement
I2C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2) [Address 00DB16]
B
0 to 4
Name
Functions
After reset R W
0
SCL frequency control bits Setup value of Standard clock High speed (CCR0 to CCR4) CCR4-CCR0 mode clock mode 0 0 to 0 2 03 04 05 06 1D 1E 1F Setup disabled Setup disabled Setup disabled Setup disabled 100 83.3 17.2 16.6 16.1 333 250 400 (See note) 166 34.5 33.3 32.3
RW
500/CCR value 1000/CCR value
...
(at = 4 MHz, unit : kHz) 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) 0: Standard clock mode 1: High-speed clock mode 0: ACK is returned. 1: ACK is not returned. 0: No ACK clock 1: ACK clock 0
RW RW RW
6 7
0 0
Note: At 400 kHz in the high-speed clock mode, the duty is as below . "0" period : "1" period = 3 : 2 In the other cases, the duty is as below. "0" period : "1" period = 1 : 1
Fig. 8.6.4 I2C Address Register
Rev. 1.0
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8.6.4 I2C Control Register
The I2C control register (address 00DA16) controls the data communication format.
(3) Bit 4: data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses. When this bit is set to "0," the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to "8.6.5 I2C Status Register," bit 1) is received, transmission processing can be performed. When this bit is set to "1," the free data format is selected, so that slave addresses are not recognized.
(1) Bits 0 to 2: bit counter (BC0-BC2)
These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become "0002" and the address data is always transmitted and received in 8 bits.
(2) Bit 3: I2C interface use enable bit (ESO)
This bit enables usage of the multimaster I2C BUS interface. When this bit is set to "0," the use disable status is provided, so the SDA and the SCL become high-impedance. When the bit is set to "1," use of the interface is enabled. When ESO = "0," the following is performed. * PIN = "1," BB = "0" and AL = "0" are set (they are bits of the I2C status register at address 00D916 ). * Writing data to the I2C data shift register (address 00D716) is disabled.
(4) Bit 5: addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is set to "0," the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address 00D816) are compared with address data. When this bit is set to "1," the 10-bit addressing format is selected, all the bits of the I2C address register are compared with address data.
(5) Bits 6 and 7: connection control bits between I 2 C-BUS interface and ports (BSEL0, BSEL1)
These bits controls the connection between SCL and ports or SDA and ports (refer to Figure 8.6.5).
"0" "1" BSEL0 SCL1/P11 SCL Multi-master I2C-BUS interface SDA "0" "1" BSEL1 SCL2/P12 "0" "1" BSEL0 SDA1/P13 "0" "1" BSEL1 SDA2/P14
Note: Set the corresponding direction register to "1" to use the port as multi-master I2C-BUS interface.
Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1
Rev. 1.0
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I2C Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D) [Address 00DA16]
B
0 to 2
Name
Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions
b0 0: 8 1: 7 0: 6 1: 5 0: 4 1: 3 0: 2 1: 1
After reset R W
0
RW
3 4 5
I2C-BUS interface use enable bit (ESO) Data format selection bit(ALS) Addressing format selection bit (10BIT SAD)
0: Disabled 1: Enabled 0: Addressing format 1: Free data format 0: 7-bit addressing format 1: 10-bit addressing format b7 b6 Connection port (See note) 0 0: None 0 1: SCL1, SDA1 1 0: SCL2, SDA2 1 1: SCL1, SDA1, SCL2, SDA2
0 0 0 0
RW RW RW RW
6, 7 Connection control bits between I2C-BUS interface and ports (BSEL0, BSEL1)
Fig. 8.6.6 I2C Control Register
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.6.5 I2C Status Register
The I2C status register (address 00D916) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the highorder 4 bits can be read out and written to.
(5) Bit 4: I2C-BUS interface interrupt request bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from "1" to "0." At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to "0" in synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the PIN bit. When the PIN bit is "0," the SCL is kept in the "0" state and clock generation is disabled. Figure 8.6.8 shows an interrupt request signal generating timing chart. The PIN bit is set to "1" in any one of the following conditions. * Executing a write instruction to the I2C data shift register (address 00D716). * When the ESO bit is "0" * At reset The conditions in which the PIN bit is set to "0" are shown below: * Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) * Immediately after completion of 1-byte data reception * In the slave reception mode, with ALS = "0" and immediately after completion of slave address or general call address reception * In the slave reception mode, with ALS = "1" and immediately after completion of address data reception
(1) Bit 0: last receive bit (LRB)
This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to "0." If ACK is not returned, this bit is set to "1." Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 00D716).
(2) Bit 1: general call detecting flag (AD0)
This bit is set to "1" when a general callV whose address data is all "0" is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to "0" by detecting the STOP condition or START condition. VGeneral call: The master transmits the general call address "0016" to all slaves.
(3) Bit 2: slave address comparison flag (AAS)
This flag indicates a comparison result of address data. s In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to "1" in one of the following conditions. * The address data immediately after occurrence of a START condition matches the slave address stored in the high-order 7 bits of the I2C address register (address 00D816). * A general call is received. s In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to "1" with the following condition. * When the address data is compared with the I2C address register (8 bits consists of slave address and RBW), the first bytes match. s The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 00D716).
(6) Bit 5: bus busy flag (BB)
This bit indicates the status of use of the bus system. When this bit is set to "0," this bus system is not busy and a START condition can be generated. When this bit is set to "1," this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (See note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to "1" by detecting a START condition and set to "0" by detecting a STOP condition. When the ESO bit of the I2C control register (address 00DA16) is "0" and at reset, the BB flag is kept in the "0" state.
(7) Bit 6: communication mode specification bit (transfer direction specification bit: TRX)
This bit decides the direction of transfer for data communication. When this bit is "0," the reception mode is selected and the data of a transmitting device is received. When the bit is "1," the transmission mode is selected and address data and control data are output into the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I2C control register (address 00DA16) is "0" in the slave reception mode is selected, the TRX bit is set to "1" ___ (transmit) if the least significant bit (R/W bit) of the address data trans___ mitted by the master is "1." When the ALS bit is "0" and the R/W bit is "0," the TRX bit is cleared to "0" (receive). The TRX bit is cleared to "0" in one of the following conditions. * When arbitration lost is detected. * When a STOP condition is detected. * When occurence of a START condition is disabled by the START condition duplication prevention function (Note). * With MST = "0" and when a START condition is detected. * With MST = "0" and when ACK non-return is detected. * At reset
(4) Bit 3: arbitration lostV detecting flag (AL)
n the master transmission mode, when a device other than the microcomputer sets the SDA to "L,", arbitration is judged to have been lost, so that this bit is set to "1." At the same time, the TRX bit is set to "0," so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to "0." When arbitration is lost during slave address transmission, the TRX bit is set to "0" and the reception mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device. VArbitration lost: The status in which communication as a master is disabled.
Rev. 1.0
37
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(8) Bit 7: Communication mode specification bit (master/slave specification bit: MST)
This bit is used for master/slave specification for data communication. When this bit is "0," the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is "1," the master is specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL. The MST bit is cleared to "0" in one of the following conditions. * Immediately after completion of 1-byte data transmission when arbitration lost is detected * When a STOP condition is detected. * When occurence of a START condition is disabled by the START condition duplication preventing function (Note). * At reset
Note: The START condition duplication prevention function disables the START condition generation, reset of bit counter reset, and SCL output, when the following condition is satisfied: a START condition is set by another master device.
I2C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00D916] B
0 1 2 3 4 5
Name
Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB)
Functions
0 : Last bit = "0 " 1 : Last bit = "1 " (See note)
After reset R W
Indeterminate 0 0
R-- R-- R-- R-- RW RW RW
0 : No general call detected 1 : General call detected (See note) 0 : Address mismatch 1 : Address match 0 : Not detected 1 : Detected (See note)
0 1 0 0
(See note) 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode
6, 7 Communication mode specification bits (TRX, MST)
Note : These bits and flags can be read out, but cannnot be written.
Fig. 8.6.7 I2C Status Register
SCL PIN
IICIRQ
Fig. 8.6.8 Interrupt Request Signal Generation Timing
Rev. 1.0
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8.6.6 START Condition Generation Method
When the ESO bit of the I2C control register (address 00DA16) is "1," execute a write instruction to the I2C status register (address 00D916) to set the MST, TRX and BB bits to "1." A START condition will then be generated. After that, the bit counter becomes "0002" and an SCL for 1 byte is output. The START condition generation timing and BB bit set timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 8.6.9 for the START condition generation timing diagram, and Table 8.6.2 for the START condition/ STOP condition generation timing table.
I2C status register write signal SCL SDA BB flag Setup time Setup time Hold time Set time for BB flag
Fig. 8.6.9 START Condition Generation Timing Diagram
8.6.7 STOP Condition Generation Method
When the ESO bit of the I2C control register (address 00DA16) is "1," execute a write instruction to the I2C status register (address 00D916) for setting the MST bit and the TRX bit to "1" and the BB bit to "0". A STOP condition will then be generated. The STOP condition generation timing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 8.6.10 for the STOP condition generation timing diagram, and Table 8.6.2 for the START condition/STOP condition generation timing table.
I2C status register write signal SCL SDA BB flag Setup time Hold time Reset time for BB flag
Fig. 8.6.10 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Timing Table Item Standard Clock Mode Setup time 5.0 s (20 cycles) (START condition) Setup time 4.25 s (17 cycles) (STOP condition) 5.0 s (20 cycles) Hold time Set/reset time 3.0 s (12 cycles) for BB flag High-speed Clock Mode 2.5 s (10 cycles) 1.75 s (7 cycles) 2.5 s (10 cycles) 1.5 s (6 cycles)
Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles.
Rev. 1.0
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8.6.8 START/STOP Condition Detect Conditions
The START/STOP condition detect conditions are shown in Figure 8.6.11 and Table 8.6.3. Only when the 3 conditions of Table 8.6.3 are satisfied, a START/STOP condition can be detected.
Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal "IICIRQ" is generated to the CPU.
8.6.9 Address Data Communication
There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats is described below.
(1) 7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00DA16) to "0." The first 7-bit address data transmitted from the master is compared with the high-order 7-bit slave address stored in the I2C address register (address 00D816). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00D816) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 8.6.12, (1) and (2).
SCL release time SCL SDA (START condition) SDA (STOP condition) Setup time Setup time Hold time
(2) 10-bit addressing format
Hold time To meet the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00DA16) to "1." An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I2C address register (address 00D816). At the time of this comparison, an address comparison between the RBW bit of the I2C address register (address 00D816) and the R/W bit which is the last bit of the address data transmitted from the master is made. In the 10-bit addressing mode, the R/W bit which is the last bit of the address data not only specifies the direction of communication for control data but also is processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00D916) is set to "1." After the second-byte address data is stored into the I2C data shift register (address 00D716), make an address comparison between the second-byte data and the slave address by software. When the address data of the 2nd bytes matches the slave address, set the RBW bit of the I2C address register (address 00D816) to "1" by software. This processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2C address register (address 00D816). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 8.6.12, (3) and (4).
Fig. 8.6.11 START Condition/STOP Condition Detect Timing Diagram
Table 8.6.3 START Condition/STOP Condition Detect Conditions Standard Clock Mode 6.5 s (26 cycles) < SCL release time 3.25 s (13 cycles) < Setup time 3.25 s (13 cycles) < Hold time High-speed Clock Mode 1.0 s (4 cycles) < SCL release time 0.5 s (2 cycles) < Setup time 0.5 s (2 cycles) < Hold time
Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles.
Rev. 1.0
40
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.6.10 Example of Master Transmission
An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. Set a slave address in the high-order 7 bits of the I2 C address register (address 00D816) and "0" in the RBW bit. Set the ACK return mode and SCL = 100 kHz by setting "8516" in the I2C clock control register (address 00DB16). Set "1016" in the I2C status register (address 00D916) and hold the SCL at the HIGH. { Set a communication enable status by setting "4816" in the I2 C control register (address 00DA16). Set the address data of the destination of transmission in the highorder 7 bits of the I 2C data shift register (address 00D716) and set "0" in the least significant bit. } Set "F016" in the I2C status register (address 00D916) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. ~ Set transmit data in the I2C data shift register (address 00D716). At this time, an SCL and an ACK clock automatically occurs. When transmitting control data of more than 1 byte, repeat step . Set "D016" in the I2C status register (address 00D916). After this, if ACK is not returned or transmission ends, a STOP condition will be generated.
8.6.11 Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, in the ACK non-return mode, using the addressing format, is shown below. Set a slave address in the high-order 7 bits of the I2C address register (address 00D816) and "0" in the RBW bit. Set the no ACK clock mode and SCL = 400 kHz by setting "2516" in the I2C clock control register (address 00DB16). Set "1016" in the I2C status register (address 00D916) and hold the SCL at the HIGH. { Set a communication enable status by setting "4816" in the I2C control register (address 00DA16). When a START condition is received, an address comparison is made. } *When all transmitted address are"0" (general call): AD0 of the I2C status register (address 00D916) is set to "1"and an interrupt request signal occurs. *When the transmitted addresses match the address set in : ASS of the I2C status register (address 00D916) is set to "1" and an interrupt request signal occurs. *In the cases other than the above: AD0 and AAS of the I2C status register (address 00D916) are set to "0" and no interrupt request signal occurs. ~ Set dummy data in the I 2C data shift register (address 00D716). When receiving control data of more than 1 byte, repeat step . When a STOP condition is detected, the communication ends.
Rev. 1.0
41
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
S
Slave address R/W
A
Data
A
Data
A/A
P
7 bits " 0" 1 to 8 bits 1 to 8 bits (1) A master-transmitter transmits data to a slave-receiver
S
Slave address R/W
A
Data
A
Data
A
P
7 bits " 1" 1 to 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter Slave address R/W 1st 7 bits Slave address 2nd byte
S
A
A
Data
A
Data
A/A
P
7 bits " 0" 8 bits 1 to 8 bits 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave address R/W 1st 7 bits Slave address 2nd byte Slave address R/W 1st 7 bits
S
A
A
Sr
Data
A
Data 1 to 8 bits
A
P
7 bits " 0" 8 bits 7 bits "1" 1 to 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit From master to slave From slave to master
Fig. 8.6.12 Address Data Communication Format
8.6.12 Precautions when using multi-master I2C-BUS interface (1) Read-modify-write instruction
The precautions when the raead-modify-write instruction such as SEB, CLB etc. is executed for each register of the multi-master I2C-BUS interface are described below. *I2C data shift register (S0) When executing the read-modify-write instruction for this register during transfer, data may become a value not intended. *I2C address register (S0D) When the read-modify-write instruction is executed for this register at detecting the STOP condition, data may become a value not ______ intended. It is because hardware changes the read/write bit (RBW) at the above timing. *I2C status register (S1) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. *I2C control register (S1D) When the read-modify-write instruction is executed for this register at detecting the START condition or at completing the byte transfer, data may become a value not intended. Because hardware changes the bit counter (BC0-BC2) at the above timing. *I2C clock control register (S2) The read-modify-write instruction can be executed for this register.
(2) START condition generating procedure using multi-master
Procedure example (The necessary conditions of the generating procedure are described as the following to ). * * --
LDA SEI BBS 5,S1,BUSBUSY BUSFREE: STA S0 LDM #$F0, S1 CLI * * BUSBUSY: CLI * *
(Taking out of slave address value) (Interrupt disabled) (BB flag confirming and branch process) (Writing of slave address value) (Trigger of START condition generating) (Interrupt enabled)
(Interrupt enabled)
Use "STA," "STX" or "STY" of the zero page addressing instruction for writing the slave address value to the I2C data shift register. Use "LDM" instruction for setting trigger of START condition generating. {Write the slave address value of above and set trigger of START condition generating of above continuously shown the above procedure example. Disable interrupts during the following three process steps: * BB flag confirming * Writing of slave address value * Trigger of START condition generating When the condition of the BB flag is bus busy, enable interrupts immediately.
Rev. 1.0
42
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
(3) RESTART condition generating procedure
Procedure example (The necessary conditions of the generating procedure are described as the following to .) Execute the following procedure when the PIN bit is "0." * * #$00, S1 -- S0 #$F0, S1 * * Select the slave receive mode when the PIN bit is "0." Do not write "1" to the PIN bit. Neither "0" nor "1" is specified for the writing to the BB bit. The TRX bit becomes "0" and the SDA pin is released. The SCL pin is released by writing the slave address value to the I 2C data shift register. Use "STA," "STX" or "STY" of the zero page addressing instruction for writing. {Use "LDM" instruction for setting trigger of RESTART condition generating. Write the slave address value of above and set trigger of RESTART condition generating of above continuously shown the above procedure example. }Disable interrupts during the following two process steps: * Writing of slave address value * Trigger of RESTART condition generating
(4) STOP condition generating procedure
Procedure example (The necessary conditions of the generating procedure are described as the following to .) * *
LDM LDA SEI STA LDM CLI
(Select slave receive mode) (Taking out of slave address value) (Interrupt disabled) (Writing of slave address value) (Trigger of RESTART condition generating) (Interrupt enabled)
SEI LDM #$C0, S1 NOP LDM #$D0, S1 CLI * *
(Interrupt disabled) (Select master transmit mode) (Set NOP) (Trigger of STOP condition generating) (Interrupt enabled)
Write "0" to the PIN bit when master transmit mode is select. Execute "NOP" instruction after setting of master transmit mode. Also, set trigger of STOP condition generating within 10 cycles after selecting of master trasmit mode. {Disable interrupts during the following two process steps: * Select of master transmit mode * Trigger of STOP condition generating
(5) Writing to I2C status register
Do not execute an instruction to set the PIN bit to "1" from "0" and an instruction to set the MST and TRX bits to "0" from "1" simultaneously. It is because it may enter the state that the SCL pin is released and the SDA pin is released after about one machine cycle. Do not execute an instruction to set the MST and TRX bits to "0" from "1" simultaneously when the PIN bit is "1." It is because it may become the same as above.
(6) Process of after STOP condition generating
Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes "0" after generating the STOP condition in the master mode. It is because the STOP condition waveform might not be normally generated. Reading to the above registers do not have the problem.
Rev. 1.0
43
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.7 PWM OUTPUT FUNCTION
This microcomputer is equipped with two 14-bit PWM (DA) and eight 8-bit PWMs (PWM0-PWM7). DA1 and DA2 have a 14-bit resolution with the minimum resolution bit width of 0.25 s and a repeat period of 4096 s (for f(XIN) = 8 MHz). PWM0-PWM7 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 s and repeat period of 1024 s (for f(XIN) = 8 MHz). Figure 8.7.1 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to DA and PWM0- PWM7 using f(XIN) divided by 2 as a reference signal.
8.7.4 Operating of 14-bit PWM
As with 8-bit PWM, set the bit 0 of PWM output control register 1 (address 00D516) to "0" (at reset, bit 0 is already set to "0" automatically), so that the PWM count source is supplied. Next, select the output polarity by bit 2 of PWM output control register 2 (address 00D616). Then, the 14-bit PWM outputs from the DA output pin by setting bit 1 of PWM output control register 1 to "0" (at reset, this bit already set to "0" automatically) to select the DA output. The output example of the 14-bit PWM is shown in Figure 8.7.3. The 14-bit PWM divides the data of the DA latch into the low-order 6 bits and the high-order 8 bits. The fundamental waveform is determined with the high-order 8-bit data "DH." A HIGH area with a length t ! DH (HIGH area of fundamental waveform) is output every short area of "t" = 256 = 64 s ( is the minimum resolution bit width of 250 ns). The HIGH level area increase interval (tm) is determined with the low-order 6-bit data "DL." The HIGH are of smaller intervals "tm" shown in Table 5 is longer by t than that of other smaller intervals in PWM repeat period "T" = 64t. Thus, a rectangular waveform with the different HIGH width is output from the DA pins. Accordingly, the PWM output changes by unit pulse width by changing the contents of the DA-H and DA-L registers. A length of entirely HIGH cannot be output, i. e. 256/256.
8.7.1 Data Setting
When outputting DA, first set the high-order 8 bits to the DA-H register (address 00CE16), then the low-order 6 bits to the DA-L register (address 00CF16). When outputting PWM0-PWM7, set 8-bit output data to the PWMi register (i means 0 to 7; addresses 00D016 to 00D416, 00F616 to 00F816).
8.7.2 Transferring Data from Registers to PWM Circuit
Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is executed at writing data to the register. The signal output from the 8-bit PWM output pin corresponds to the contents of this register. Also, data transfer from the DA register (addresses 00CE16 and 00CF16) to the 14-bit PWM circuit is executed at writing data to the DA-L register (address 00CF16). Reading from the DA-H register (address 00CE16) means reading this transferred data. Accordingly, it is possible to confirm the data being output from the DA output pin by reading the DA register.
8.7.5 Output after Reset
At reset, the output of ports P60-P63 and P00-P03 are in the highimpedance state, and the contents of the PWM register and the PWM circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register.
8.7.3 Operating of 8-bit PWM
The following explains PWM operation. First, set the bit 0 of PWM output control register 1 (address 00D516) to "0" (at reset, bit 0 is already set to "0" automatically), so that the PWM count source is supplied. PWM0-PWM3 are also used as pins P60-P63, PWM4-PWM7 are also used as ports P00-P03, respectively. For PWM0-PWM3, set the corresponding bits of the ports P6 direction register to "1" (output mode). For PWM4-PWM7, set those of the port P0 direction register to "1." And select each output polarity by bit 3 of PWM output control register 2 (address 00D616). Then, for PWM0-PWM5, set bits 2 to 7 of PWM output control register 1 to "1" (PWM output). For PWM6 and PWM7, set bits 0 and 1 of PWM output control register 2 to "1." The PWM waveform is output from the PWM output pins by setting these registers. Figure 8.7.2 shows the 8-bit PWM timing. One cycle (T) is composed of 256 (28) segments. The 8 kinds of pulses, relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. Refer to Figure 8.7.2 (a). The 8-bit PWM outputs waveform which is the logical sum (OR) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit PWM register. Several examples are shown in Figure 8.7.2 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are selected by changing the contents of the PWM register. A length of entirely HIGH output cannot be output, i.e. 256/256.
Table 8.7.1 Relation Between the Low-order 6-bit Data and Highlevel Area Increase Interval Low-order 6 bits of Data Area Longer by than That of Other tm (m = 0 to 63) 000000 000001 000010 000100 001000 010000 100000
LSB
Nothing m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 m = 1, 3, 5, 7, ................................. 57, 59, 61, 63
Rev. 1.0
44
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Data bus
DA-H register (Address : 00CE16) b7 DA latch (14 bits)
MSB LSB
b0
DA-L register (See note) (Address : 00CF16)
8 6
6 14
PN2 14-bit PWM circuit
PN4 PW1
DA DA
XIN
1/2 PW0
PWM timing generating circuit
PWM register ( Address : 00D0 16)
b7
8
b0
PN3 8-bit PWM circuit
P60 PW2 P61 PW3 P62 PW4 P63 PW5 P00
D60
PWM0
D61
PWM1
PWM1 register (Address : 00D1
16)
D62
PWM2
PWM2 register (Address : 00D2
16)
D63
PWM3
PWM3 register (Address : 00D3
16)
D00
PWM4
Selection gate : Connected to black colored side when reset. Pass gate Inside of with the others. is as same contents
PWM4 register (Address : 00D4
16)
PW6 P02 PW7 P02 PN0 P03 PN1 D03 PWM7 D02 PWM6 D02 PWM5
PWM5 register (Address : 00F6
16)
PWM6 register (Address : 00D7
16)
PW F PWM output control register 1 PN FPWM output control register 2
PWM7 register (Address : 00F8
16)
D0 F Port P0 direction register D6 F Port P6 direction register Note: The DA-L register also functions as the low-order 6 bits of the DA latch.
Fig. 8.7.1 PWM Block Diagram
Rev. 1.0
45
46
60 80 12 0 15 0 18 0 21 0 24 0 25 0 25 5 22 0 23 0 19 0 20 0 16 0 17 0 13 0 14 0 90 10 0 11 0 70
54 58 62 66 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 70 74 78 82 86 90
13579
20
30
40
50
Bit 7
Fig. 8.7.2 PWM Timing
52 60 92 12 4 15 6 18 8 22 0 25 2 22 8 23 6 24 4 19 6 20 4 21 2 16 4 17 2 18 0 13 2 14 0 14 8 10 0 10 8 11 6 68 76 84 56 88 12 0 15 2 18 4 21 6 23 2 20 0 16 8 13 6 10 4 72 24 8 80 11 2 14 4 17 6 20 8 24 0 96 16 0 22 4 64 19 2 12 8
2
6
10 14
18
22
26
30 34 38
42
46 50
Bit 6
4
12
20
28
36
44
Bit 5
8
24
40
Bit 4
16
48
Bit 3
32
Bit 2
Bit 1
Bit 0
(a) Pulses showing the weight of each bit
0016 (0)
0116 (1)
1816 (24)
FF16 (255)
t T = 256 t PWM output t = 4 s T = 1024 s f(XIN) = 8 MHz
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
(b) Example of 8-bit PWM
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Set "2C16" to DA-H register.
Set "2816" to DA-L register.
b7 b6 b5 b4 b3 b2 b1 b0 [DA-H 0 0 1 0 1 1 0 0 DH register] At writing of DA-L b13 [DA latch] 0 0 1 0 1 1 0 b6 b5 0 1 0 1
b7 b6 b5 b4 b3 b2 b1 b0 [DA-L register] 1 0 1 0 0 0 DL
At writing of DA-L b0 0 0 0
These bits decide HIGH level area of fundamental waveform.
HIGH level area of fundamental waveform Minimum resolution bit width 0.25 s
These bits decide smaller interval "tm" in which HIGH leval area is [HIGH level area of fundamental waveform + ].
!
High-order 8-bit value of DA latch
Fundamental waveform
Waveform of smaller interval "tm" specified by low-order 6 bits 0.25 s!44 0.25 s!45 0.25 s 14-bit 2C 2B 2A ... 03 02 01 00 PWM output 8-bit counter FF FE FD ... D6 D5 D4 D3 ... 02 01 00
14-bit ... 03 02 01 00 PWM output 2C 2B 2A 8-bit counter FF FE FD ... D6 D5 D4 D3 ... 02 01 00
Fundamental waveform of smaller interval "tm" which is not specified by low-order 6 bits is not changed. 0.25 s!44 = 0.25 s
14-bit PWM output t 0 Low-order 6-bit output of DA latch Repeat period T = 4096 s @ t 1 t 2 t 3 t 4 t 5 t9 5 t0 6 t1 6 t2 6 t3 6
Fig. 8.7.3 14-bit PWM Timing (f(XIN) = 8 MHz)
Rev. 1.0
47
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
PWM Output Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 1 (PW) [Address 00D516] B Name Functions 0 DA, PWM count source 0 : Count source supply 1 : Count source stop selection bit (PW0) 0 : DA output 1 DA/PN4 selection bit 1 : PN4 output (PW1) 2 P60/PWM0 output selection bit (PW2) 3 P61/PWM1 output selection bit (PW3) 4 P62/PWM2 output selection bit (PW4) 5 P63/PWM3 output selection bit (PW5) 6 P00/PWM4 output selection bit (PW6) 7 P01/PWM5 output selection bit (PW7) 0: P60 output 1: PWM0 output 0: P61 output 1: PWM1 output 0: P62 output 1: PWM2 output 0: P63 output 1: PWM3 output 0: P00 output 1: PWM4 output 0: P01 output 1: PWM5 output After reset R W 0 RW 0 0 0 0 0 0 0 RW RW RW RW RW RW RW
Fig. 8.7.4 PWM Output Control Register 1
PWM Output Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 2 (PN) [Address 00D6 B Name 0 P02/PWM6 output selection bit (PN0) 1 2 3 4 P03/PWM7 output selection bit (PN1) DA output polarity selection bit (PN2) PWM output polarity selection bit (PN3) DA general-purpose output bit (PN4) Functions 0 : P02 1 : PWM6 output 0 : P03 1 : PWM7 output 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Output LOW 1 : Output HIGH
16]
After reset R W
0 0 0 0 0
RW RW RW RW RW
5 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are "0." 7
0
R--
Fig. 8.7.5 PWM Output Control Register 2
Rev. 1.0
48
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.8 A-D COMPARATOR
A-D comparator consists of 6-bit D-A converter and comparator. A-D comparator block diagram is shown in Figure 8.8.1. The reference voltage "Vref" for D-A conversion is set by bits 0 to 5 of the A-D control register (address 00EF16). The comparison result of the analog input voltage and the reference voltage "Vref" is stored in bit 4 of the A-D mode register (address 00EE16). For A-D comparison, set "0" to corresponding bits of the direction register to use ports as analog input pins. Write the data for select of analog input pins to bits 0 to 2 of the A-D control register 1 and write the digital value corresponding to Vref to be compared to the bits 0 to 5 of the A-D control register. The voltage comparison starts by writing to the A-D control register 2, and it is completed after 16 machine cycles (NOP instruction ! 8).
Data bus
A-D mode register
Bits 0 to 2
Comparator control
A-D1 A-D2 A-D3 A-D4 A-D5 A-D6 A-D7 A-D8
A-D mode register Analog signal switch Comparator Bit 4 Bit 5 Bit 4
A-D control register Bit 3 Bit 2 Bit 1 Bit 0
Switch tree
Resistor ladder
Fig. 8.8.1 A-D Comparator Block Diagram
Rev. 1.0
49
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
A-D Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
A-D mode register (ADM) [Address 00EE16]
B
0 to 2
Name
Analog input pin selection bits (ADM0 to ADM2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions
b0 0 : A-D1 1 : A-D2 0 : A-D3 1 : A-D4 0 : A-D5 1 : A-D6 0 : A-D7 1 : A-D8
After reset R W
0
RW
3 4 5 to 7
This bit is a write disable bit. When this bit is read out, the value is "0." Storage bit of comparison result (ADM4) 0: Input voltage < reference voltage 1: Input voltage > reference voltage
0 Indeterminate 0
R-- R-- R--
Nothing is assigned. This bits are write disable bits. When these bits are read out, the values are "0."
Fig. 8.8.2 A-D Mode Register
A-D Control Register
b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (ADC) [Address 00EF16]
B 0 to 5
Name D-A converter set bits (ADC0 to ADC5) b5 0 0 0 b4 0 0 0 b3 0 0 0
Functions b2 0 0 0 b1 0 0 1 b0 0 : 1/128Vcc 1 : 3/128Vcc 0 : 5/128Vcc
After reset 0
RW RW
1 1 1
1 1 1
1 1 1
1 1 1
0 1 1
1 : 123/128Vcc 0 : 125/128Vcc 1 : 127/128Vcc 0 R--
6, 7 Nothing is assigned. These bits are write disable bits. When these bits are reed out, the values are " 0."
Fig. 8.8.3 A-D Control Register
Rev. 1.0
50
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.9 ROM CORRECTION FUNCTION
This can correct program data in ROM. Up to 2 addresses can be corrected, a program for correction is stored in the ROM correction memory in RAM as the top address. The ROM correction vectors are 2 vectors. Vector 1 : address 02C016 Vector 2 : address 02E016 Set the address of the ROM data to be corrected into the ROM correction address register. When the value of the counter matches the ROM data address in the ROM correction vector as the top address, the main program branches to the correction program stored in the ROM memory for correction. To return from the correction program to the main program, the op code and operand of the JMP instruction (total of 3 bytes) are necessary at the end of the correction program. The ROM correction function is controlled by the ROM correction enable register.
Notes 1: Specify the first address (op code address) of each instruction as the ROM correction address. 2: Use the JMP instruction (total of 3 bytes) to return from the correction program to the main program. 3: Do not set the same ROM correction address to vectors 1 and 2. 4: Only M37212M8-XXXSP and M37212EFSP/FP have ROM correction function.
ROM correction address 1 (high-order) 021716 ROM correction address 1 (low-order) 021816
ROM correction address 2 (high-order) 021916 ROM correction address 2 (low-order) 021A16
Fig. 8.9.1 ROM Correction Address Registers
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
00
ROM correction enable register (RCR) [Address 021B16]
B
0
1
Name
Vector 1 enable bit (RC0)
Vector 2 enable bit (RC1)
Functions
0: Disabled 1: Enabled
0: Disabled 1: Enabled
After reset R W
0 0
0 0
RW RW RW R--
2, 3 Fix these bits to "0."
4 to 7
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
Fig. 8.9.2 ROM Correction Enable Register
Rev. 1.0
51
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.10 OSD FUNCTIONS
Table 8.10.1 outlines the OSD functions. This microcomputer incorporates an OSD control circuit of 24 characters ! 2 lines. OSD is controlled by the CRT control register. Up to 256 kinds of characters can be displayed. The colors can be specified for each character and up to 4 kinds of colors can be displayed on one screen. A combination of up to 8 colors can be obtained by using each output signal (R, G, and B). Characters are displayed in a 12 ! 16 dots configuration to obtain smooth character patterns (refer to Figure 8.10.1). The following shows the procedure how to display characters on the CRT screen. Write the display character code in OSD RAM. Specify the display color by using the color register. Write the color register in which the display color is set in OSD RAM. { Specify the vertical position by using the vertical position register. Specify the character size by using the character size register. } Specify the horizontal position by using the horizontal position register. ~ Write the display enable bit to the designated block display flag of the CRT control register. When this is done, the OSD starts according to the input of the VSYNC signal.
Table 8.10.1 Features of Each Display Mode
Parameter Functions
Number of display characters Dot structure Kinds of characters Kinds of character sizes Attribute Character font coloring Character background coloring OSD output Display position Display expansion (multiline display)
24 characters ! 2 lines 12 ! 16 dots 256 kinds 3 kinds Border (black) 1 screen : 8 kinds (per character unit) 1 screen : 8 kinds (per character unit) R, G, B Horizontal: 64 levels, Vertical: 128 levels Possible
Rev. 1.0
52
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
The OSD circuit has an extended display mode. This mode allows multiple lines (3 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software. Figure 8.10.1 shows the configuration of OSD character. Figure 8.10.2 shows the block diagram of the OSD circuit. Figure 8.10.3 shows the CRT control register.
12 dot s
16 dot s
Fig. 8.10.1 Configuration of OSD Character Display Area
Rev. 1.0
53
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Clock for OSD OSC1 OSC2 H S Y N C VS Y N C
Display oscillation circuit
C ontolr gi t r f rO S D r e se s o OSD Control circuit Horizontal position register Vertical position register Character size register Color register CRT control register CRT port control register (address 00E016) (addresses 00E116, 00E216) (addresses 00E416) (addresses 00E616 to 00E916) (address 00EA16) (address 00EC16)
OSD RAM 10 bis ~24 characters ~2 lines t
OSD ROM 12 dots ~16 dots ~256 characters
Shift register 12-bit Output circuit Shift register 12-bit
R
G
B
O U T1
O U T2
Data bus
Fig. 8.10.2 Block Diagram of OSD Circuit
Rev. 1.0
54
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
CRT Control Register
b7 b6 b5 b4 b3 b2 b1 b0 CRT control register (CC) [Address 00EA16]
B 0 1 2 3 to 6 7
Name All-blocks display control bit (CC0) (See note) Block 1 display control bit (CC1) Block 2 display control bit (CC2)
Functions 0 : All-blocks display off 1 : All-blocks display on 0 : Block 1 display off 1 : Block 1 display on 0 : Block 2 display off 1 : Block 2 display on
After reset R W 0 0 0 0 RW RW RW R--
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." P10/OUT2 pin switch bit (CC7) 0 : P10 1 : OUT2
0
RW
Note: Display is controlled by logical product (AND) between the all-blocks display control bit and each block control bit.
Fig. 8.10.3 CRT Control Register
Rev. 1.0
55
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.10.1 Display Position
The display positions of characters are specified in units called a "block." There are 2 blocks, blocks 1 and 2. Up to 24 characters can be displayed in each block (refer to "8.10.3 Memory for OSD"). The display position of each block can be set in both horizontal and vertical directions by software. The display start position in the horizontal direction can be selected for all blocks in common from 64-step display positions in units of 4TC (TC = OSD oscillation cycle). The display start position in the vertical direction for each block can be selected from 128-step display positions in units of 4 scanning lines.
Blocks are displayed in conformance with the following rules: * Block 2 is displayed after the display of block 1 is completed (Figure 8.10.4 (a)). * When the display position of block 1 is overlapped with that of block 2 (Figure 8.10.4 (b)), the block 1 is displayed on the front. * When another block display position appears while one block is displayed (Figure 8.10.4 (c)),only block 1 is displayed. Similarly, when multiline display, block 1 is displayed after the display of block 2 is completed.
HR CV1 Block 1 C V2 Block 2 (a) Example when each block is separated
HR CV1 = CV2 Block 1 (Block 2 is not displayed) (b) Example when block 2 overlaps with block 1
HR CV1 CV2
Block 1 Block 2 CV1 Block 1 (second) Not displayed Not displayed
(c) Example when block 2 overlaps in process of block 1 Notes 1: CV1 or CV2 indicates the vertical display start position of display block 1 or 2. 2: HR indicates the horizontal display start position of display block 1 or 2.
Fig. 8.10.4 Display Position
Rev. 1.0
56
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
The vertical display start position is determined by counting the horizontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are positive polarity (negative polarity), it starts to count the rising edge (falling edge) of HSYNC signal from after fixed cycle of rising edge (falling edge) of VSYNC signal. So interval from rising edge (falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) for avoiding jitter. The polarity of HSYNC and VSYNC signals can select with the CRT port control register (address 00EC16).
8 machine cycles or more VSYNC signal input 0.25 to 0.50 [s] ( at f(XIN) = 8MHz) VSYNC control signal in microcomputer Period of counting HSYNC signal HSYNC signal input 8 machine cycles or more 1 2 3 4 5
(See note 2)
Not count When bits 0 and 1 of the CRT port control register (address 00EC16) are set to "1" (negative polarity) Notes 1 : The vertical position is determined by counting falling edge of HSYNC signal after rising edge of VSYNC control signal in the microcomputer. 2 : Do not generate falling edge of HSYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. 3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or more.
Fig. 8.10.5 Supplement Explanation for Display Position
Rev. 1.0
57
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
The vertical display start position for each block can be set in 512 steps (where each step is 1TH (TH: HSYNC cycle)) as values "0016" to "7F16" in vertical position register i (i = 1 and 2) (addresses 00E116 and 00E216) The vertical position register i is shown in Figure 8.10.6.
Vertical Position Register i
b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register i (CVi) (i = 1 and 2) [Addresses 00E1 16, 00E216]
B 0 to 6 7
Name Vertical display start positions (CVi : CVi0 to CVi6)
Functions 128 steps (0016 to 7F16)
After reset
RW
Indeterminate R W
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
0
R--
Fig. 8.10.6 Vertical Position Register i
Rev. 1.0
58
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
The horizontal display start position is common to all blocks, and can be set in 64 steps (where 1 step is 4TC, TC being the OSD oscillation cycle) as values "0016" to "3F16" in bits 0 to 5 of the horizontal position register (address 00D116). The horizontal position register is shown in Figure 8.10.7.
Horizontal Position Register
b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HR) [Address 00E0 16]
B 0 to 5
Name Horizontal display start positions (HR0 to HR5)
Functions 64 steps (0016 to 3F16)
After reset 0 0
RW RW R--
6, 7 Nothing is assigned. These bits are write disable bits. When thses bits are read out, the values are "0."
Fig. 8.10.7 Horizontal Position Register
Rev. 1.0
59
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.10.2 Character Size
The size of characters to be displayed can be from 3 sizes for each block. Use the character size register (address 00E416) to set a character size. The character size of block 1 can be specified by using bits 0 and 1 of the character size register; the character size of block 2 can be specified by using bits 2 and 3. Figure 8.10.8 shows the character size register. The character size can be selected from 3 sizes: minimum size, medium size and large size. Each character size is determined by the number of scanning lines in the height (vertical) direction and the oscillating cycle for display (TC) in the width (horizontal) direction. The minimum size consists of [1 scanning line] ! [1TC]; the medium size consists of [2 scanning lines] ! [2TC]; and the large size consists of [3 scanning lines] ! [3TC]. Table 8.10.2 shows the relation between the set values in the character size register and the character sizes.
Character Size Register
b7 b6 b5 b4 b3 b2 b1 b0 Character size register (CS) [Address 00E4 16]
B
Name
Functions 00 : Minimum size 01 : Medium size 10 : Large size 11 : Do not set. 00 : Minimum size 01 : Medium size 10 : Large size 11 : Do not set.
After reset
RW
0, 1 Character size of block 1 selection bits (CS10, CS11) 2,3 Character size of block 2 selection bits (CS20,CS21) 4 to 7
Indeterminate R W
Indeterminate R W
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
0
R--
Fig. 8.10.8 Character Size Register
Rev. 1.0
60
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Minimum
Medium
Large
Horizontal display start position
Fig. 8.10.9 Display Start Position of Each Character Size (Horizontal Direction)
Table. 8.10.2 Relation between Set Values in Character Size Register and Character Sizes
Set values of character size register CSn1 0 0 1 1 CSn0 0 1 0 1
Character Width (horizontal) direction size TC: oscillating cycle for display Minimum Medium Large This is not available 1 TC 2 TC 3 TC
Height (vertical) direction scanning lines 1 2 3
Note: The display start position in the horizontal direction is not affected by the character size. In other words, the horizontal display start position is common to all blocks even when the character size varies with each block (refer to Figure 8.10.9).
Rev. 1.0
61
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.10.3 Clock for OSD
As a clock for display to be used for OSD, it is possible to select one of the following 4 types. * Main clock supplied from XIN pin * Main clock supplied from XIN pin divided by I.5 * Clock from the ceramic resonator or the LC or oscillator from the pins OSC1 and OSC2 * Clock from the ceramic resonator or the quartz-crystal oscillator supplied from the pins OSC1 and OSC2. This OSD clock for each block can be selected by the CRT clock selection register (address 00ED16). When selecting the main clock, set the oscillation frequency to 8 MHz.
CRT Clock Selection Register
b7 b6 b5 b4 b3 b2 b1 b0
000000
CRT clock selection register (CK) [Address 00ED16]
B
Name
Functions
After reset R W 0 RW
0, 1 CRT clock Functions b1 b0 selection bits 0 0 The clock for display is supplied by connecting RC (CK0,CK1) or LC across the pins OSC1 and OSC2. 0 1 Since the main clock is used as the OSD oscillation clock for display, the oscillation frequency frequency is limited. Because of this, = f(XIN) the character size in width (horizontal) 0 OSD oscillation direction is also limited. In this case, frequency pins OSC1 and OSC2 are also used = f(XIN)/1.5 as input ports P36 and P37 respectively. 1 The clock for OSD is supplied by connecting the following across the pins OSC1 and OSC2. * a ceramic resonator only for OSD and a feedback resistor * a quartz-crystal oscillator only for OSD and a feedback resistor (See note)
1
1
2 to 7 Fix these bits to "0."
0
RW
Note: It is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins XN and XOUT. I
Fig. 8.10.10 Block Diagram of OSD Selection Circuit
Rev. 1.0
62
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.10.4 Memory for OSD
There are 2 types of memory for OSD : OSD ROM (addresses 1000016 to 11FFF16) used to store character dot data and OSD RAM (addresses 060016 to 06B716) used to specify the characters and colors to be displayed.
(1) OSD ROM (addresses 1000016 to 11FFF16)
The dot pattern data for OSD characters is stored in OSD ROM. To specify the kinds of the character font, it is necessary to write the character code (Table 8.10.3) into the OSD RAM. The OSD ROM has a capacity of 8K bytes. Since 32 bytes are required for 1 character data, the ROM can stores up to 256 kinds of characters. The OSD ROM space is broadly divided into 2 areas. The [vertical 16 dots] ! [horizontal (left side) 8 dots] data of display characters are stored in addresses 1000016 to 107FF16 and 1100016 to 117FF16 ; the [vertical 16 dots] ! [horizontal (right side) 4 dots] data of display characters are stored in addresses 1080016 to 10FFF16 and 1180016 to 11FFF16 (refer to Figure 8.10.11). Note however that the highorder 4 bits in the data to be written to addresses 1080016 to 10FFF16 and 1180016 to 11FFF16 must be set to "1" (by writing data "FX16"). Data of the character font is specified shown in Figure 8.10.11.
10XX016 or 11XX016
10XXF16 or 11XXF16
b7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0
0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0
0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0
b0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0
10XX016 +80016 or 11XX016 +80016
10XXF16 +80016 or 11XXF16 +80016
b7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
b3 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Fig. 8.10.11 Character Font Data Storing Address
Rev. 1.0
63
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Table 8.10.3 Character Code List (Partially Abbreviated)
Character code Character data storage address Left 8 dots lines 1000016 to 1000F16 1001016 to 1001F16 1002016 to 1002F16 1003016 to 1003F16
:
(2) OSD RAM (addresses 060016 to 06B716)
The OSD RAM is allocated at addresses 060016 to 06B716, and is divided into a display character code specification part, and color code specification part for each block. Table 8.10.4 shows the contents of the OSD RAM. For example, to display 1 character position (the left edge) in block 1, write the character code in address 060016, write the color code at 068016. The structure of the OSD RAM is shown in Figure 8.10.12.
Right 4 dots lines 1080016 to 1080F16 1081016 to 1081F16 1082016 to 1082F16 1083016 to 1083F16
:
0016
0116
0216
0316
:
7E16
107E016 to 107EF16 107F016 to 107FF16 1100016 to 1100F16 1101016 to 1101F16
:
10FE016 to 10FEF16 10FF016 to 10FFF16 1180016 to 1180F16 1181016 to 1181F16
:
7F16
8016
8116
:
FD16
117D016 to 117DF16 117E016 to 117EF16 117F016 to 117FF16
11FD016 to 11FDF16 11FE016 to 11FEF16 11FF016 to 11FFF16
FE16
FF16
Table 8.10.4 Contents of OSD RAM
Block Display Position (from left) 1st character 2nd character 3rd character : 22nd character 23rd character 24th character Not used 1st character 2nd character 3rd character : 22nd character 23rd character 24th character Character Code Specification 060016 060116 060216 : 061516 061616 061716 061816 : 061F16 062016 062116 062216 : 063516 063616 063716 Color Specification 068016 068116 068216 : 069516 069616 069716 069816 : 069F16 06A016 06A116 06A216 : 06B516 06B616 06B716
Block 1
Block 2
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Block 1 [Character specification] 1st character : 0600 16 to 24th character : 061716 Character code Specify 256 characters ("00 16" to "FF16") [Color specification] 1st character : 0680 16 to 24th character : 069716 Color register specification 0 0 : Specifying color register 0 0 1 : Specifying color register 1 1 0 : Specifying color register 2 1 1 : Specifying color register 3 Block 2 [Character specification] 1st character : 0620 16 to 24th character : 063716 Character code Specify 256 characters ("00 16" to "FF16") [Color specification] 1st character : 06A016 to 24th character : 06B7 16 Color register specification 0 0 : Specifying color register 0 0 1 : Specifying color register 1 1 0 : Specifying color register 2 1 1 : Specifying color register 3 1 0 7 0 1 0 7 0
Fig. 8.10.12 Bit structure of OSD RAM
Rev. 1.0
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MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.10.5 Color Register
The color of a displayed character can be specified by setting the color to one of the 4 registers (CO0 to CO3: addresses 00E616 to 00E916) and then specifying that color register with the OSD RAM. There are 3 color outputs; R, G and B. By using a combination of these outputs, it is possible to set 8 colors. However, since only 4 color registers are available, up to 4 colors can be disabled at one time. R, G and B outputs are set by using bits 1 to 3 in the color register. Bit 5 is used to specify whether a character output or blank output. Bits 4, 6 and 7 are used to specify character background color. Figure 8.10.12 shows the color register.
Color Register i
b7 b6 b5 b4 b3 b2 b1 b0 Color regist er i (COi) (i = 0 to 3) [Addresses 00E616 to 00E916]
B 0 1 2 3 4 5 6 7
Name
@
Functions
After reset R W 0 R--
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." B signal output selection bit (COi1) G signal output selection bit (COi2) R signal output selection bit (COi3) 0: No character is output 1: Character is output 0: No character is output 1: Character is output 0: No character is output 1: Character is output
Indeterminate R W
Indeterminate R W
Indeterminate R W
B signal output (background) 0: No background color is output Indeterminate R W selection bit (COi4) (See note 1) 1: Background color is output OUT1 signal output control bit (COi5) (See notes 1, 2) 0: Character is output 1: Blank is output
Indeterminate R W
0: No background color is output Indeterminate R W G signal output (background) selection bit (COi6) (See note 1) 1: Background color is output R signal output (background) 0: No background color is output Indeterminate R W selection bit (COi7) (See note 2) 1: Background color is output
Notes 1: When bit 5 ="0" and bit 4 = "1," there is output same as a character or border output from pin OUT1. Do not set bit 5 = "0" and bit 4 = "0." 2: When only bit 7 ="1" and bit 5 "0," there is output from pin OUT2.
Fig. 8.10.13 Color Register i
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Table 8.10.5 Display Example of Character Background Coloring (When Green Is Set for a Character and Blue Is Set for Background Color)
Border selection register Color register i G output
MD0 COi7 COi6 COi5 COi4 COi3 COi2 COi1
B output
OUT1 output
Character output Green
OUT2 output
0
0
!
0
1 0 (Note 1)
1
0
No output Same output as character A
Video signal and character color (green) are not mixed.
No output (See note 2)
Green 0 1 ! 0 1 0 1 0 No output Same output as Video signal and character color (green) are not mixed. character A Green 0 0 0 1 0 0 1 0 No output Blank output
TV image of character background is not displayed.
Blank output
No output (See note 2)
Green 0 0 0 1 1 0 1 0 Background color Blank output Blue
TV image of character background is not displayed.
No output (See note 2)
1
!
!
Border output (Black) 0 1 0 1 0 No output Border output (Black)
Green No output (See note 2)
Video signal and character color (green) are not mixed.
Green 1 0 0 1 0 0 1 0 No output Blank output Black
TV image of character background is not displayed.
No output (See note 2)
1
0
0
1
1
0
1
0
Background color - border
Border output (Black)
Green No output (See note 2)
Blue Blank output
TV image of character background is not displayed.
Notes 1 : When COi5 = "0" and COi4 = "1," there is output same as a character or border output from the OUT1 pin. Do not set COi5 = "0" and COi4 = "0." 2 : When only COi7 = "1" and COi5 = "0," there is output from pin OUT2. 3 : The portion "A" in which character dots are displayed is not mixed with any TV video signal. 4 : The wavy-lined arrows in the Table denote video signals. 5 : n : 0 to 3, ! : 0 or 1
Rev. 1.0
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.10.6 Border
An border of 1 clock (1 dot) equivalent size can be added to a character to be displayed in both horizontal and vertical directions. The border is output from the OUT pin. In this case, set bit 5 of a color register to "0" (character is output). Border can be specified in units of block by using the border selection register (address 00E516). Figure 8.10.14 shows the border selection register. Table 8.10.6 shows the relationship between the values set in the border selection register and the character border function.
Fig. 8.10.15 Example of Border
Border Selection Register
b7 b6 b5 b4 b3 b2 b1 b0 Border selection register (MD) [Address 00E5 16]
B 0 1 2 3 to 7
Name
Functions
After reset R W
Block 1 OUT1 output 0 : Same output as R, G, B is output Indeterminate R W border selection bit (MD10) 1 : Border output Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." 0 R--
Block 2 OUT1 output 0 : Same output as R, G, B is output Indeterminate R W border selection bit (MD20) 1 : Border output Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 0 R--
Fig. 8.10.14 Border Selection Register
Table 8.10.6 Relationship between Set Value in Border Selection Register and Character Border Function
Border selection register MDn0 0 Functions Example of output R, G, B output OUT1 output R, G, B output OUT1 output
Ordinary
1
Border including character
Rev. 1.0
68
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.10.7 Multiline Display
This microcomputer can ordinarily display 2 lines on the CRT screen by displaying 2 blocks at different vertical positions. In addition, it can display up to 16 lines by using OSD interrupts. An OSD interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scanning line exceeds the block.
Note: An OSD interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to off display by the display control bit of the CRT control register (address 00EA16), an OSD interrupt request does not occur (refer to Figure 8.10.16).
Block 1 (on display) Block 2 (on display) Block 1' (on display) Block 2' (on display)
"OSD interrupt request" "OSD interrupt request" "OSD interrupt request" "OSD interrupt request"
Block 1 (on display) Block 2 (on display) Block 1' (off display) Block 2' (off display)
"OSD interrupt request" "OSD interrupt request" No "OSD interrupt request" No "OSD interrupt request"
On display (OSD interrupt request occurs at the end of block display)
Off display (OSD interrupt request does not occur at the end of block display)
Fig. 8.10.16 Note on Occurence of OSD Interrupt
Rev. 1.0
69
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.10.8 OSD Output Pin Control
The OSD output pins R, G, B and OUT1 can also function as ports P52-P55. Set corresponding bit of the port P5 direction register (address 00CB16) to "0" to specify these pins as OSD output pins, or set it to "1" to specify it as a general-purpose port P5. The OUT2 can also function as port P10. Set bit 0 of the CRT port control register (address 00EC16) to "1" (output mode). After that, set bit 7 of the CRT port control register to "1" to specify the pin as OSD output pin, or set it to "0" to specify as port P10. The input polarity of the HSYNC, VSYNC and output polarity of signals R, G, B, OUT1 and OUT2 can be specified with the CRT port control register (address 00EC) . Set a bit to "0" to specify positive polarity; set it to "1" to specify negative polarity (refer to Figure 8.11.13). The CRT port control register is shown in Figure 8.10.17.
CRT Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0 CRT port control register (CRTP) [Address 00EC16]
B 0 1 2 3 4 5 6 7
Name HSYNC input polarity switch bit (HSYC) VSYNC input polarity switch bit (VSYC)
Functions 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input
After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW
R/G/B output polarity switch 0 : Positive polarity output 1 : Negative polarity output bit (R/G/B) OUT2 output polarity switch bit (OUT2) OUT1 output polarity switch bit (OUT1) R signal output switch bit (OP5) G signal output switch bit(OP6) B signal output switch bit(OP7) 0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0 : R signal output 1 : MUT E signal output 0 : G signal output 1 : MUT E signal output 0 : B signal output 1 : MUT E signal output
Fig. 8.10.17 CRT Port Control Register
Rev. 1.0
70
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.10.9 Raster Coloring Function
An entire screen (raster) can be colored by setting the CRT port control register. Since each of the R, G, B, OUT1, and OUT2 pins can be switched to raster coloring output, 8 raster colors can be obtained. When the character color/the character background color overlaps with the raster color, the color (R, G, B, OUT1, OUT2), specified for the character color/the character background color, takes priority of the raster color. This ensures that character color/character background color is not mixed with the raster color. The example of raster coloring is shown in Figure 8.10.18.
: Character color "RED" (R + OUT1 + OUT2) : Border color "BLACK" (OUT1 + OUT2) : Background color "MAGENTA" (R + B + OUT1 + OUT2) : Raster color "BLUE" (B + OUT1 + OUT2)
A
A'
HSYNC OUT1 OUT2 R G B
Signals across A-A'
Fig. 8.10.18 Example of Raster Coloring
Rev. 1.0
71
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.11 SOFTWARE RUNAWAY DETECT FUNCTION
This microcomputer has a function to decode undefined instructions to detect a software runaway. When an undefined op-code is input to the CPU as an instruction code during operation, the following processing is done. The CPU generates an undefined instruction decoding signal. The device is internally reset because of occurrence of the undefined instruction decoding signal. As a result of internal reset, the same reset processing as in the case of ordinary reset operation is done, and the program restarts from the reset vector. Note, however, that the software runaway detecting function cannot be invalid.
SYNC
Address
PC
?
01,S
01,S-1
01,S-2
FFFE16
FFFF16
ADH, ADL
Data
?
PCH
PCL
PS Reset sequence
ADL
ADH
Undefined instruction decoding signal occurs.Internal reset signal occurs. ?
: Undefined instruction decode : Invalid PC : Program counter S : Stack pointer ADL, ADH: Jump destination address of reset
Fig. 8.11.1 Sequence at Detecting Software Runaway Detection
Rev. 1.0
72
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.12. RESET CIRCUIT
When the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and the power source voltage is 5 V 10 %, hold the RESET pin at LOW for 2 s or more, then return is to HIGH. Then, as shown in Figure 8.12.2, reset is released and the program starts form the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address. The internal state of microcomputer at reset are shown in Figures 8.2.3 to 8.2.6. An example of the reset circuit is shown in Figure 8.12.1. The reset input voltage must be kept 0.6 V or less until the power source voltage surpasses 4.5 V. Poweron 4 .5 V Power source voltage 0 V
Reset input voltage 0 V
0 .6 V
Vcc
1 5
M51 953AL
RESET
4 3 0.1 F
Vss Microcomputer Fig. 8.12.1 Example of Reset Circuit
XIN RESET Internal RESET SYNC Address Data ? ? 32768 count of XIN clock cycle (See note 3) ? ?
01, S
01, S-1 01, S-2
FFFE
FFFF
ADH, ADL
Reset address from the vector table ? ? ? ADL ADH
Notes 1 : f(XIN) and f() are in the relation : f(XIN) = 2*f (). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, "FF16" is set in timer 3 and "0716" is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal.
Fig. 8.12.2 Reset Sequence
Rev. 1.0
73
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.13 CLOCK GENERATING CIRCUIT
The built-in clock generating circuit is shown in Figure 8.13.3. When the STP instruction is executed, the internal clock stops at HIGH. At the same time, timers 3 and 4 are connected by hardware and "FF16" is set in timer 3 and "0716" is set in the timer 4. Select f(XIN)/16 as the timer 3 count source (set bit 0 of the timer mode register 2 to "0" before the execution of the STP instruction). Moreover, set the timer 3 and timer 4 interrupt enable bits to disabled ("0") before execution of the STP instruction). The oscillator restarts when external interrupt is accepted. However, the internal clock keeps its HIGH until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. When the WIT instruction is executed, the internal clock stops in the HIGH but the oscillator continues running. This wait state is released when an interrupt is accepted (See note). Since the oscillator does not stop, the next instruction can be executed at once. When returning from the stop or the wait state, to accept an interrupt, set the corresponding interrupt enable bit to "1" before executing the STP or the WIT instructions.
Note: In the wait mode, the following interrupts are invalid. * VSYNC interrupt * OSD interrupt * All timers interrupts using TIM2 and TIM3 pins input as count source * All timers interrupts using f(XIN)/2 as count source * All timers interrupts using f(XIN)/4092 as count source * f(XIN)/4096 interrupt * Multi-master I2C-BUS interface interrupt
Microcomputer XIN XOUT
CIN
COUT
Fig. 8.13.1 Ceramic Resonator Circuit Example
Microcomputer XIN
Vcc External oscillation circuit Vss
A circuit example using a ceramic resonator (or a quartz-crystal oscillator) is shown in Figure 8.13.1. Use the circuit constants in accordance with the resonator manufacture's recommended values. A circuit example with external clock input is shown in Figure 8.13.2. Input the clock to the XIN pin, and open the XOUT pin.
Fig. 8.13.2 External Clock Input Circuit Example
Interrupt request S Interrupt disable flag I Reset
WIT instruction
Q
Q
S
Reset
S
Q
R
R
Selection gate : Connected to black side at reset. T34M : Timer 34 mode register
STP instruction
R
STP instruction
Internal clock
1/2
1/8 T34M0 T34M2
Timer 3
Timer 4
XIN
XOUT
Fig. 8.13.3 Clock Generating Circuit Block Diagram
Rev. 1.0
74
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
8.14 DISPLAY OSCILLATION CIRCUIT
The OSD oscillation circuit has a built-in clock oscillation circuits, so that a clock for OSD can be obtained simply by connecting an LC, an RC, a ceramic resonator, or a quartz-crystal oscillator across the pins OSC1 and OSC2. Which of the sub-clock or the OSD oscillation circuit is selected by setting bits 0 and 1 of the CRT clock selection register (address 00ED16).
8.16 ADDRESSING MODE
The memory access is reinforced with 17 kinds of addressing modes. Refer to SERIES 740 User's Manual for details.
8.17 MACHINE INSTRUCTIONS
There are 71 machine instructions. Refer to SERIES 740 User's Manual for details.
9. PROGRAMMING NOTES
* The divide ratio of the timer is 1/(n+1). * Even though the BBC and BBS instructions are executed immediately after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. * After the ADC and SBC instructions are executed (in the decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. * An NOP instruction is needed immediately after the execution of a PLP instruction. * In order to avoid noise and latch-up, connect a bypass capacitor ( 0.1F) directly between the VCC pin-VSS pin and the VCC pin- CNVSS pin, using a thick wire.
OSC1
OSC2
L C1 C2
Fig. 8.14.1 Display Oscillation Circuit
8.15 AUTO-CLEAR CIRCUIT
When a power source is supplied, the auto-clear function will operate by connecting the following circuit to the RESET pin.
Circuit example 1
Vcc
RESET
Vss
Circuit example 2
RESET
Vcc
Vss
Note : Make the level change from "L" to "H" at the point at which the power source voltage exceeds the specified voltage.
Fig. 8.15.1 Auto-clear Circuit Example
Rev. 1.0
75
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
10. ABSOLUTE MAXIMUM RATINGS
Symbol VCC, AVCC VI VI Parametear Power source voltage VCC Input voltage CNVSS Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P42, OSC1, XIN, ______ HSYNC, VSYNC, RESET Output voltage P10-P14, P20-P17, P30, P31, P40, P41, R, G, B, OUT1, DA XOUT, OSC2 Output voltage P00-P07, P60-P63 Circuit current R, G, B, OUT1, P10-P14, P20-P27, P30, P31, DA Circuit current R, G, B, OUT1, P06, P07, P10, P20-P23, P30, P31, P40, P41, DA Circuit current P11-P14 Circuit current P00-P07, P60-P63 Circuit current P24-P27 Power dissipation Operating temperature Storage temperature Conditions All voltages are based on VSS. Output transistors are cut off. Ratings -0.3 to 6 -0.3 to 6 -0.3 to VCC + 0.3 Unit V V V
VO
-0.3 to VCC + 0.3
V
VO IOH IOL1 IOL2 IOL3 IOL4 Pd Topr Tstg
-0.3 to 13 0 to 1 (See note 1) 0 to 2 (See note 2) 0 to 6 (See note 2) 0 to 1 (See note 2) 0 to 10 (See note 3) 550 -10 to 70 -40 to 125
V mA mA mA mA mA mW C C
Ta = 25 C
11. RECOMMENDED OPERATING CONDITIONS (Ta = -10 C to 70 C, VCC = 5 V 10 %, unless otherwise noted)
Symbol VCC VSS VIH1 Parameter Power source voltage (See note 4), During CPU, OSD operation Power source voltage HIGH input voltage P00-P07, P10-P17, P20-P27, P30-P37, ______ SIN, SCLK, HSYNC, VSYNC, RESET, XIN, OSC1, TIM2, TIM3, INT1-INT3 HIGH input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) LOW input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P42 LOW input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) ______ LOW input voltage (See note 6) HSYNC, VSYNC, RESET, TIM2, TIM3, INT1-INT3, XIN, OSC1, SIN, SCLK HIGH average output current (See note 1) R, G, B, OUT1, DA, P10-P14, P20-P27, P30, P31 LOW average output current (See note 2) R, G, B, OUT1, DA, P10, P20-P23, P30, P31, P40, P41 LOW average output current (See note 2) P11-P14 LOW average output current (See note 2) P00-P07, P60-P63 LOW average output current (See note 3) P24-P27 Oscillation frequency (for CPU operation) (See note 5) XIN Oscillation frequency (for OSD) OSC1 Input frequency TIM2, TIM3 Input frequency SCLK Input frequency SCL1, SCL2 Min. 4.5 0 0.8VCC Limits Typ. 5.0 0 Max. 5.5 0 VCC Unit V V V
VIH2 VIL1 VIL2 VIL3 IOH IOL1 IOL2 IOL3 IOL4 f(XIN) fosc fhs1 fhs2 fhs3
0.7VCC 0 0 0
VCC 0.4 VCC 0.3 VCC 0.2 VCC 1 2 6 1 10 8.1 8.0 100 1 400
V V V V mA mA mA mA mA MHz MHz kHz MHz kHz
7.9 5.0
8.0
Rev. 1.0
76
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
12. ELECTRIC CHARACTERISTICS (VCC = 5 V 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = -10 C to 70 C, unless otherwise noted)
Symbol ICC Parameter Power source current System operation Test conditions VCC = 5.5 V, f(XIN) = 4 MHz VCC = 5.5 V, f(XIN) = 8 MHz OSD OFF OSD ON OSD OFF OSD ON VCC = 5.5 V, f(XIN) = 0 VCC = 4.5 V IOH = -0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 4.5 V IOL = 10.0 mA VCC = 4.5 V IOL = 3 mA IOL = 6 mA VCC = 4.5 V IOL = 0.5 mA VCC = 5.0 V VCC = 5.0 V 0.5 0.5 Limits Min. Typ. 10 20 20 30 Max. 20 40 40 60 300 Unit mA 1 A V V 2 Test circuit
VOH VOL
Stop mode HIGH output voltage R, G, B, OUT1, DA, P10-P14, P20-P27, P30, P31 LOW output voltage R, G, B, OUT1, DA, P10, P20-P23, P30, P31, P40, P41 LOW output voltage P24-P27 LOW output voltage P11-P14 LOW output voltage P00-P07, P60-P63
______
2.4 0.4
3.0 0.4 0.6 0.4 0.7 1.3 V
RESET VT+ - VT- Hysteresis Hysteresis (See note 6) HSYNC, VSYNC, TIM2, TIM3, INT1-INT3, SCL1, SCL2, SDA1, SDA2, SIN, SCLK ______ HIGH input leak current RESET, P10-P17, P20-P27, IIZH P30-P37, P40-P42, HSYNC, VSYNC ______ LOW input leak current RESET, P00-P07, P10-P17, IIZL P20-P27, P30-P37, P40-P42, P60-P63, HSYNC, VSYNC HIGH input leak current P00-P07, P60-P63 IOZH RBS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) I2C-BUS*BUS
3
VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VI = 0 V VCC = 5.5 V VI = 12 V VCC = 4.5 V
5 5
A A 4
10 130
A
5 6
Notes 1: The total current that flows out of the IC must be 20 mA or less. 2: The total input current to IC (IOL1 + IOL2 + IOL3) must be 30 mA or less. 3: The total average input current for ports P24-P27 to IC must be 20 mA or less. 4: Connect 0.1 F or more capacitor externally between the power source pins VCC-VSS so as to reduce power source noise. Also connect 0.1 F or more capacitor externally between the pins VCC-CNVSS. 5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 6: P15, P32-P35 have the hysteresis when these pins are used as interrupt input pins or timer input pins. P11-P14 have the hysteresis when these pins are used as multi-master I2C-BUS interface ports. P40-P42 have the hysteresis when these pins are used as serial I/O pins. 7: Pin names in each parameter is described as below. (1) Dedicated pins: dedicated pin names. (2) Duble-/triple-function ports * When the same limits: I/O port name. * When the limits of functins except ports are different from I/O port limits: function pin name.
Rev. 1.0
77
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
+ Power source voltage
1
A I cc XIN 8.00 MHz OSC1 XOUT Vcc
2
4.5 V
V cc
Each output pin
OSC2
VOH Vss
Vss
IOH or IOL
V
or VOL
Pin VCC is made the operation state and is measured the current, with a ceramic resonator.
After setting each output pin to HIGH level when measuring VOH and to LOW level when measuring VOL, each pin is measured.
3
5.0 V
4
5.5 V
Vcc
Vcc
IIZH or IIZL A
Each input pin
Each input pin
Vss
Vss
5.5 V
5
6
4.5V
Vcc IOZH Each output pin A
12 V
Vcc SCL1 or SDA1 A RBS IBS
SCL2 or SDA2
Vss
Vss
VBS
After setting each output pin OFF state, each pin is measured
RBS = VBS/IBS
Fig.12.1 Measure Circuits
Rev. 1.0
78
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
13. A-D COMPARISON CHARACTERISTICS
(VCC = 5 V 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = 25 C, unless otherwise noted) Symbol -- -- Resolution Absolute accuracy Parameter Test conditions Min. 0 Limits Typ. 1 Max. 6 2 Unit bits LSB
14. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS
Symbol tBUF tHD; STA tLOW tR tHD; DAT tHIGH tF tSU; DAT tSU; STA tSU; STO Parameter Bus free time Hold time for START condition LOW period of SCL clock Rising time of both SCL and SDA signals Data hold time HIGH period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition Standard clock mode High-speed clock mode Unit Min. Max. Min. Max. 4.7 1.3 s 4.0 0.6 s 4.7 1.3 s 1000 20+0.1Cb 300 ns 0 0 0.9 s 4.0 0.6 s 300 20+0.1Cb 300 ns 250 100 ns 4.7 0.6 s 4.0 0.6 s
Note: Cb = total capacitance of 1 bus line
SDA tHD;STA tSU;STO
tBUF tLOW P SCL S
tR
tF Sr P
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
S : Start condition Sr : Restart condition P : Stop condition
Fig.14.1 Definition Diagram of Timing on Multi-master I2C-BUS
Rev. 1.0
79
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
15. PROM PROGRAMMING METHOD
The built-in PROM of the One Time PROM version (blank) and the built-in EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter. Product M37212EFSP M37212EFFP Name of Programming Adapter PCA7406 PCA7420
The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process nor any following processes. To ensure proper operation after programming, the procedure shown in Figure 15.1 is recommended to verify programming.
Programming with PROM programmer
Screening (Caution) (150C for 40 hours)
Verification with PROM programmer
Functional check in target device
Caution : The screening temperature is far higher than the storage temperature. Never expose to 150C exceeding 100 hours.
Fig. 15.1 Programming and Testing of One Time PROM Version
Rev. 1.0
80
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
16. DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: * Mask ROM Order Confirmation Form * Mark Specification Form * Data to be written to ROM, in EPROM form (32-pin DIP Type 27C101, three identical copies) or FDK
Rev. 1.0
81
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
17. MASK CONFIRMATION FORM
GZZ-SH55-23B < 91A0 >
Mask ROM number
Note : Please fill in all items marked V. ) Issuance signature Company name Customer Date issued Date : TEL (
Submitted by Supervisor
V
V1. Confirmation Three EPROMs are required for each pattern if this order is performed by EPROMs. One floppy disk is required for each pattern if this order is performed by a floppy disk.
Ordering by EPROMs If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs.
Checksum code for entire EPROM EPROM type (indicate the type used)
27C101 EPROM address 000016 Product nameASCII code: 000F16 'M37212M4-' C00016
(hexadecimal notation)
Data ROM(16K)
1FFFF16
(1)
Set "FF16" in the shaded area.
82
6543210987654321 654321098765432 6543210987654321 6543210987654321 1 6543210987654321
FFFF16 1000016 107FF16 1080016 10FFF16 1100016 117FF16 1180016 11FFF16 1200016
Character ROM1-a Character ROM2-a Character ROM1-b Character ROM2-b
(1/3)
Rev. 1.0
Receipt
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37212M4-XXXSP MITSUBISHI ELECTRIC
Date:
Section head Supervisor signature signature
6543210987654321 6543210987654321 6543210987654321 6543210987654321
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
GZZ-SH55-23B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37212M4-XXXSP MITSUBISHI ELECTRIC
(2) Write the ASCII codes that indicate the product name of "M37212M4-" to addresses 000016 to 000F16.
Addresses 000016 to 000F16 store the product name. Address ASCII codes `M37212M4-' are listed on the right. 000016 The addresses and data are in hexadecimal notation. 000116 000216 Note: If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Please make sure the data is written correctly. 000316 000416 000516 000616 000716 `M' = 4D16 `3' = 3316 `7' = 3716 `2' = 3216 `1' = 3116 `2' = 3216 `M' = 4D16 `4' = 3416 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 `-' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
Ordering by floppy disk We will produce masks based on the mask files generated by the mask file generating utility. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk. The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files must be 1 in one floppy disk. File code Mask file name (hexadecimal notation) .MSK (equal or less than eight characters)
V2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill the appropriate mark specification form (52P4B for M37212M4-XXXSP) and attach to the mask ROM confirmation form.
V3. Comments
(2/3)
Rev. 1.0
83
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
GZZ-SH55-23B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37212M4-XXXSP MITSUBISHI ELECTRIC
Inputting the character ROM Input the character ROM data by dividing it into character ROM1 and character ROM2.
The structure of character ROM ( divided into 12 516 dots font) Example Character code O1A16O (Note) Write the character code "00 16" to "7F16" to Addresses 10000 16 to 10FFF16. Write the character code "80 16" to "FF16" to Addresses 11000 16 to 11FFF16.
Character ROM1
Character ROM2
b7 b6 b5 b4 b3 b2 b1 b0 0 1 2 3 4 5 6 7 8 9 A B C D E F Example 101A016 to 101AF16 0 016 0 416 0416 0A16 0A16 1 116 1 116 1 116 2 016 2 016 3 F16 4 016 4 016 4 016 0 016 0 016 0 1 2 3 4 5 6 7 8 9 A B C D E F
b7 b6 b5 b4 b3 b2 b1 b0 F016 F016 F016 F016 F016 F016 F016 F016 F816 F816 F816 F416 F416 F416 F016 F016
F16
Example 109A016 to 109AF16
(3/3)
Rev. 1.0
84
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
GZZ-SH55-24B < 91A0 >
Mask ROM number
Note : Please fill in all items marked V. ) Issuance signature Company name Customer Date issued Date : TEL (
Submitted by Supervisor
V
V1. Confirmation Specify the name of the product being ordered. Three EPROMs are required for each pattern if this order is performed by EPROMs. One floppy disk is required for each pattern if this order is performed by a floppy disk. Microcomputer name : M37212M6-XXXSP M37212M6-XXXFP
Ordering by EPROMs If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM EPROM type (indicate the type used)
27C101 EPROM address
Receipt
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37212M6-XXXSP/FP MITSUBISHI ELECTRIC
Date:
Section head Supervisor signature signature
(hexadecimal notation)
A00016
1FFFF16
(1)
Set "FF16" in the shaded area.
Rev. 1.0
85
76543210987654321 6543210987654321 76543210987654321 76543210987654321 76543210987654321 7
FFFF16 1000016 107FF16 1080016 10FFF16 1100016 117FF16 1180016 11FFF16 1200016
76543210987654321 76543210987654321 76543210987654321 76543210987654321
Data ROM(24K) Character ROM1-a Character ROM2-a Character ROM1-b Character ROM2-b
000016 000F16
Product nameASCII code: 'M37212M6-'
(1/3)
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
GZZ-SH55-24B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37212M6-XXXSP/FP MITSUBISHI ELECTRIC
(2) Write the ASCII codes that indicate the product name of "M37212M6-" to addresses 000016 to 000F16.
Addresses 000016 to 000F16 store the product name. ASCII codes `M37212M6-' are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 Note: If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Please make sure the data is written correctly. 000416 000516 000616 000716 `M' = 4D16 `3' = 3316 `7' = 3716 `2' = 3216 `1' = 3116 `2' = 3216 `M' = 4D16 `6' = 3616 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 `-' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
Ordering by floppy disk We will produce masks based on the mask files generated by the mask file generating utility. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk. The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files must be 1 in one floppy disk.
File code Mask file name
(hexadecimal notation) .MSK (equal or less than eight characters)
V2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill the appropriate mark specification form (52P4B for M37212M6-XXXSP , 80P6N for M37212M6-XXXFP) and attach to the mask ROM confirmation form.
V3. Comments
(2/3)
Rev. 1.0
86
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
GZZ-SH55-24B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37212M6-XXXSP/FP MITSUBISHI ELECTRIC
Inputting the character ROM Input the character ROM data by dividing it into character ROM1 and character ROM2.
The structure of character ROM(divided into 12 516 dots font) Example Character code O1A16O (Note) Write the character code "00 16 " to "7F16" to Addresses 10000 16 to 10FFF16. Write the character code "80 16 " to "FF16" to Addresses 11000 16 to 11FFF16.
Character ROM1
Character ROM2
b7 b6 b5 b4 b3 b2 b1 b0 0 1 2 3 4 5 6 7 8 9 A B C D E F Example 101A016 to 101AF16 0 016 0 416 0416 0A16 0A16 1 116 1 116 1 116 2 016 2 016 3 F16 4 016 4 016 4 016 0 016 0 016 Example 0 1 2 3 4 5 6 7 8 9 A B C D E F
b7 b6 b5 b4 b3 b2 b1 b0 F016 F016 F016 F016 F016 F016 F016 F016 F816 F816 F816 F416 F416 F416 F016 F016
F16
109A016 to 109AF16
(3/3)
Rev. 1.0
87
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
GZZ-SH55-42B < 91A0 >
Mask ROM number
Note : Please fill in all items marked V. ) Issuance signature Company name Customer Date issued Date : TEL (
Submitted by Supervisor
V
V1. Confirmation Three EPROMs are required for each pattern if this order is performed by EPROMs. One floppy disk is required for each pattern if this order is performed by a floppy disk.
Ordering by EPROMs If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Checksum code for entire EPROM EPROM type (indicate the type used)
27C101 EPROM address
(hexadecimal notation)
800016 FFFF16 1000016 107FF16 1080016 10FFF16 1100016 117FF16 1180016 11FFF16 1200016 1FFFF16
(1)
Set "FF16" in the shaded area.
88
76543210987654321 76543210987654321 76543210987654321 76543210987654321
000016 000F16
Product nameASCII code: 'M37212M8-'
Data ROM(32K) Character ROM1-a Character ROM2-a Character ROM1-b Character ROM2-b
(1/3)
Rev. 1.0
Receipt
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37212M8-XXXSP MITSUBISHI ELECTRIC
Date:
Section head Supervisor signature signature
76543210987654321 76543210987654321 76543210987654321 76543210987654321 76543210987654321
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
GZZ-SH55-42B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37212M8-XXXSP
(2)
Write the ASCII codes that indicate the product name of "M37212M8-" to addresses 000016 to 000F16.
Addresses 000016 to 000F16 store the product name. ASCII codes `M37212M8-' are listed on the right. The addresses and data are in hexadecimal notation. Address 000016 000116 000216 000316 000416 000516 000616 000716 `M' = 4D16 `3' = 3316 `7' = 3716 `2' = 3216 `1' = 3116 `2' = 3216 `M' = 4D16 `8' = 3816 Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 `-' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
Note: If the name of the product contained in the EPROMs does not match the name on the mask ROM confirmation form, the ROM processing is disabled. Please make sure the data is written correctly.
Ordering by floppy disk We will produce masks based on the mask files generated by the mask file generating utility. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk. The submitted floppy disk must be 3.5-inch 2HD type and DOS/V format. And the number of the mask files must be 1 in one floppy disk. File code Mask file name (hexadecimal notation) .MSK (equal or less than eight characters)
V2. Mark specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill the appropriate mark specification form (52P4B for M37212M8-XXXSP) and attach to the mask ROM confirmation form.
V3. Comments
(2/3)
Rev. 1.0
89
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
GZZ-SH55-42B < 91A0 >
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37212M8-XXXSP MITSUBISHI ELECTRIC
Inputting the character ROM Input the character ROM data by dividing it into character ROM1 and character ROM2.
The structure of character ROM (divided into 12 516 dots font) Example Character code O1A16O (Note) Write the character code "0016" to "7F16" to addresses 1000016 to 10FFF16. Write the character code "8016" to "FF16" to addresses 11000 16 to 11FFF16.
Character ROM1
Character ROM2
b7 b6 b5 b4 b3 b2 b1 b0 0 1 2 3 4 5 6 7 8 9 A B C D E F Example 101A016 to 101AF16 0 016 0 416 0416 0A16 0A16 1 116 1 116 1 116 2 016 2 016 3 F16 4 016 4 016 4 016 0 016 0 016 Example 0 1 2 3 4 5 6 7 8 9 A B C D E F
b7 b6 b5 b4 b3 b2 b1 b0 F016 F016 F016 F016 F016 F016 F016 F016 F816 F816 F816 F416 F416 F416 F016 F016
F16
109A016 to 109AF16
(3/3)
Rev. 1.0
90
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
18. MARK SPECIFICATION FORM
Rev. 1.0
91
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
80P6N (80-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark
64
41 40
65
Mitsubishi IC catalog name
Mitsubishi product number (6-digit, or 7-digit)
80 1 24
25
B. Customer's Parts Number + Mitsubishi IC Catalog Name
64
41 40
65
80 1 24
25
Customer's Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Notes 1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's parts number can be up to 14 alphanumeric characters for capital letters, hyphens, commas, periods and so on.
C. Special Mark Required
64
41 40
65
80 1 24
25
Notes1 : If special mark is to be printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated technically as close as possible. Mitsubishi product number (6-digit, or 7-digit) and Mask ROM number (3-digit) are always marked for sorting the products. 2 : If special character fonts (e,g., customer's trade mark logo) must be used in Special Mark, check the box below. For the new special character fonts, a clean font original (ideally logo drawing) must be submitted. Special character fonts required
Rev. 1.0
92
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
19. ONE TIME PROM VERSION M37212EFSP/FP MARKING
M37212EFSP XXXXXXX
XXXXXXX is mitsubishi lot number
M37212EFFP XXXXXXX
XXXXXXX is mitsubishi lot number
Rev. 1.0
93
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
20. APPENDIX Pin Configuration (TOP VIEW)
HSYNC VSYNC P60/PWM0 P61/PWM1 P62/PWM2 P63/PWM3 P00/PWM4 P01/PWM5 P02/PWM6 P03/PWM7 P42/SIN/A-D5 P41/SCLK/A-D6 P40/SOUT(/IN)/A-D7 DA P35/INT2/A-D4 P34/INT1 P33/TIM3 P32/TIM2 P24 P25 P26 P27 CNVSS XIN XOUT VSS
1 2 3 4 5
52 51 50 49 48
P52/R P53/G P54/B P55/OUT1 P20 P21 P22 P23 P04 P05 P06 P07 P10/OUT2/A-D8 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/INT3/A-D1 P16/A-D2 P17/A-D3 P30 P31 RESET OSC1/P36 OSC2/P37 VCC
M37212M4/M6/M8-XXXSP, M37212EFSP
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
Outline 52P4B
Rev. 1.0
94
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
P04 P05 P06 P07 P10/OUT2/A-D8 NC P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 NC
P15/INT3/A-D1 P16/A-D2 P17/A-D3
47 46 45
P22 P23
NC NC NC
NC
64
63
62
61
60
59
58
57
56
54
53
52
51
50
49
48
44
43
42
P21 NC P20 P55/OUT1 P54/B P53/G P52/R NC NC HSYNC VSYNC P60/PWM0 P61/PWM1 P62/PWM2 NC P63/PWM3
55
41
NC NC NC NC
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
20
40 39 38 37 36 35 34
P30 NC P31 RESET OSC1/P36 OSC2/P37 VCC NC NC VSS XOUT XIN CNVSS P27 NC NC
M37212M6-XXXFP, M37212EFFP
33 32 31 30 29 28 27 26 25
21 22 23
10
11
12
13
14
15
16
17
18
Outline 80P6N-A
Rev. 1.0
95
P40/SOUT(/IN)/A-D7 DA P35/INT2/A-D4 P34/INT1 P33/TIM3
NC NC NC NC P00/PWM4 P01/PWM5 P02/PWM6 P03/PWM7 NC P42/SIN/A-D5 P41/SCLK/A-D6
P32/TIM2 P24 P25 P26 NC NC NC NC
19
24
1
2
3
4
5
6
7
8
9
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Memory Map
s M37212M4/M8-XXXSP, M37212M6-XXXSP/FP
000016 M37212M6XXXSP/FP RAM (384 bytes) M37212M4XXXSP RAM (320 bytes) 00BF16 00C016 00FF16 010016 017F16 01BF16 Zero page SFR area OSD ROM (8K bytes) 11FFF16 1000016
Not used
Not used OSD RAM (96 bytes) (See note) 060016 06B716 Not used
M37212M6XXXSP/FP ROM (24K bytes)
A00016 C00016
M37212M4XXXSP ROM (16K bytes) FF0016 FFDE16 FFFF16
Interrupt vector area
Special page 1FFFF16 Note: Refer to Table 8.10.3 OSD RAM.
Rev. 1.0
96
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
s M37212M8-XXXSP, M37212EFSP/FP
000016 00BF16 00C016 00FF16 010016 Zero page SFR area OSD ROM (8K bytes) 11FFF16 1000016
M37212EFSP RAM (1280 bytes)
M37212M8XXXSP RAM (576 bytes)
01FF16 021716 021B16
Not used 2 page register Not used
02C016 02E016 033F16 05FF16 060016
ROM correction function Vector 1: address 02C016 Vector 2: address 02E016
Not used
OSD RAM (96 bytes) (See note) M37212EFSP ROM (62K bytes)
06B716 Not used 080016 800016
M37212M8XXXSP ROM (32K bytes) FF0016 FFDE16 FFFF16
Interrupt vector area
Special page 1FFFF16 Note: Refer to Table 8.10.3 OSD RAM
Rev. 1.0
97
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Memory Map of Special Function Register (SFR)
s SFR area (addresses C016 to DF16)
Bit allocation :
Name
State immediately after reset 0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
Function bit
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address Register Bit allocation
b7
State immediately after reset
b0 b7 b0
C016 Port P0 (P0) C116 Port P0 direction register (D0) C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16
Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) Port P4 (P4) Port P4 direction register (D4) Port P5 (P5) Port P5 direction register (D5) Port P6 (P6) DA-H register (DA-H) DA-L register (DA-L) PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN) I2C data shift register (S0) I2C address register (S0D) I2C status register (S1) I2 C control register (S1D) I2C clock control register (S2) Serial I/O mode register (SM) Serial I/O register (SIO)
D7 D6 D5 PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 P N4 P N3 P N2 P N1 P N0 D4 D3 D2 D1 D0
P55 P55 SEL P54 P53 P52 P31D P30D P41 P40 P41D P40D
0 0 0
0 0 0
0 0 ?
P54 P53 P52 SEL SEL SEL P63 P62
0 1
0 1 0 0 ?
P61 P60
1
1
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW MST TRX BB PIN AL AAS AD0 LRB
0
0
0
BSEL1 BSEL0 10BIT ALS ESO BC2 BC1 BC0 SAD KF ACK ACT MAST CCR4 CCR3 CCR2 CCR1 CCR0 BI ODE
SM6 SM5
0
SM3 SM2 SM1 SM0
? 0016 ? 0016 ? 0016 ? 0016 00 00 ?? 0016 0F16 0F16 ? ?? ? ? ? ? ? 0016 0016 ? 0016 10 0016 0016 0016 ? ? ?
? ? ?
? ? 0
? ? 0
?
?
?
0
0
?
Rev. 1.0
98
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
s SFR area (addresses E016 to FF16)
Bit allocation :
Name
State immediately after reset 0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
Function bit
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Register
b7 Horizontal position register (HR) Vertical position register 1 (CV1) Vertical position register 2 (CV2) Character size register (CS) Border selection register (MD) Color register 0 (CO0) Color register 1 (CO1) Color register 2 (CO2) Color register 3 (CO3) CRT control register (CC) CRT port control register (CRTP)
Bit allocation
HR5 HR4 HR3 HR2 HR1 HR0 CV16 CV15 CV14 CV13 CV12 CV11 CV10 CV26 CV25 CV24 CV23 CV22 CV21 CV20
State immediately after reset
b0 b7 b0
0 0 0 0
? ? 0 0
? ? 0 0
CS21 CS20 CS11 CS10 MD20 CO07 CO06 CO05 CO04 CO03 CO02 CO01 CO17 CO16 CO15 CO14 CO13 CO12 CO11 CO27 CO26 CO25 CO24 CO23 CO22 CO21 CO37 CO36 CO35 CO34 CO33 CO32 CO31 MD10
CC7
CC2 CC1 CC0
OP7 OP6 OP5 OUT1 OUT2 R/G/B VSYC HSYC
CRT clock selection register (CK) 0 A-D mode register (ADM) A-D control register (ADC) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer 12 mode register (T12M) Timer 34 mode register (T34M) PWM5 register (PWM5) PWM6 register (PWM6) PWM7 register (PWM7) Interrupt input polarity register (RE) 0
0
0
0
ADM4
0
0
CK1 CK0
ADM2 ADM1 ADM0
0
0
0
ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
0
T12M4 T12M3 T12M2 T12M1 T12M0
T34M5 T34M4 T34M3 T34M2 T34M1 T34M0
RE5 RE4 RE3
0
CM2
1 CPU mode register (CM) Interrupt request register 1 (IREQ1) IT3R
Interrupt request register 2 (IREQ2) 0 Interrupt control register 1 (ICON1) IT3E Interrupt control register 2 (ICON2)
1
1
1
MSR CK 0
1
0
0
IICR VSCR OSDR TM4R TM3R TM2R TM1R
S1R IT2R IT1R
IICE VSCE OSDE TM4E TM3E TM2E TM1E
0
0
MSE
0
S1E IT2E IT1E
?
0
0
0016 ?? ?? 0016 0? 00 0016 0016 0016 0016 0016 0016 0016 0016 ?0 0016 FF16 0716 FF16 0716 0016 0016 ? ? ? 0016 ? FC16 0016 0016 0016 00
? ? ? ?
? ? ? 0
? ? ? ?
0
0
0
0
0
0
Rev. 1.0
99
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
s 2 page register area (addresses 21716 to 21B16)
Bit allocation :
Name
State immediately after reset 0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
Function bit
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address Register Bit allocation
b7
State immediately after reset
b0 b7 b0
21716 ROM correction address 1 (high-order) 21816 ROM correction address 1 (low-order) 21916 ROM correction address 2 (high-order) 21A16 ROM correction address 2 (low-order) 21B16 ROM correction enable register (RCR)
0
0
RCR1RCR0
0016 0016 0016 0016 0016
Note: Only M37212M8-XXXSP and M37212EFSP/FP have 2 page register.
Rev. 1.0
100
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Internal State of Processor Status Register and Program Counter at Reset
Bit allocation :
Name
State immediately after reset 0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset
Function bit
: : No function bit
0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Register
b7 Processor status register (PS) Program counter (PCH) Program counter (PCL)
Bit allocation N V T B D I Z C
State immediately after reset
b0 b7 b0
?????1?? Contents of address FFFF16 Contents of address FFFE16
Rev. 1.0
101
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Structure of Register
The figure of each register structure describes its functions, contents at reset, and attributes as follows:

CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 00 11
Bit position Bit attributes(Note 2) Values immediately after reset release (Note 1)
CPU mode register (CPUM) (CM) [Address 00FB16] Name 0, 1 Processor mode bits (CM0, CM1) B Functions
b1 b0
A f t er r e R W RW 0
0 0 1 1
0: Single-chip mode 1: 0: Not available 1: 1 1 1 0 RW RW RW RW
2
Stack page selection bit (See note) (CM2)
0: 0 page 1: 1 page
3, 4 Fix these bits to "1." 5 Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is "1." b7 b6 Clock switch bits 6, 7 (CM6, CM7) 0 0: f(XIN) = 8 MHz 0 1: f(XIN) = 12 MHz 1 0: f(XIN) = 16 MHz 1 1: Do not set : Bit in which nothing is assigned
Notes 1: Values immediately after reset release 0 ******************"0" after reset release 1 ******************"1" after reset release Indeterminate***Indeterminate after reset release 2: Bit attributes******The attributes of control register bits are classified into 3 types : read-only, write-only and read and write. In the figure, these attributes are represented as follows : R******Read W******Write W ******Write enabled R ******Read enabled - ******Read disabled - ******Write disabled V ******"0" can be set by software, but "1" cannot be set.
Rev. 1.0
102
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Addresses 00C116, 00C316, 00C516
Port Pi Direction Register
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (Di) (i=0,1,2) [Addresses 00C1 16, 00C316, 00C516]
B 0 1 2 3 4 5 6 7
Name Port Pi direction register
Functions 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode
After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW
Address 00C716
Port Pi Direction Register
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (Di) (i = 3, 4) [Address 00C716, 00C916]
B 0 1
Name Port Pi direction register
Functions 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode
After reset R W 0 0 RW RW
2 to 7 Nothing is assigned. These bits are write disable bits. indeterminate R -- When these bits are read out, the values are indeterminate.
Rev. 1.0
103
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Address 00CB16
Port P5 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direction register (D5) [Address 00CB16]
b
Name
Functions
After reset R W 0 0 0 0 0 R-- RW RW RW RW
0, 1 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 2 3 4 5 Port P52 output signal selection bit (P52SEL) Port P53 output signal selection bit (P53SEL) Port P54 output signal selection bit (P54SEL) Port P55 output signal selection bit (P55SEL) 0 : R signal output 1 : Port P52 output 0 : G signal output 1 : Port P53 output 0 : B signal output 1 : Port P54 output 0 : OUT1 signal output 1 : Port P55 output
6,7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0.
Indeterminate R --
Address 00D516
PWM Output Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 1 (PW) [Address 00D516] B Name Functions 0 DA, PWM count source 0 : Count source supply 1 : Count source stop selection bit (PW0) 0 : DA output 1 DA/PN4 selection bit 1 : PN4 output (PW1) 2 P60/PWM0 output selection bit (PW2) 3 P61/PWM1 output selection bit (PW3) 4 P62/PWM2 output selection bit (PW4) 5 P63/PWM3 output selection bit (PW5) 6 P00/PWM4 output selection bit (PW6) 7 P01/PWM5 output selection bit (PW7) 0: P60 output 1: PWM0 output 0: P61 output 1: PWM1 output 0: P62 output 1: PWM2 output 0: P63 output 1: PWM3 output 0: P00 output 1: PWM4 output 0: P01 output 1: PWM5 output After reset R W 0 RW 0 0 0 0 0 0 0 RW RW RW RW RW RW RW
Rev. 1.0
104
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Address 00D616
PWM Output Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 2 (PN) [Address 00D6 B Name 0 P02/PWM6 output selection bit (PN0) 1 2 3 4 P03/PWM7 output selection bit (PN1) DA output polarity selection bit (PN2) PWM output polarity selection bit (PN3) DA general-purpose output bit (PN4) Functions 0 : P02 1 : PWM6 output 0 : P03 1 : PWM7 output 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Output LOW 1 : Output HIGH
16]
After reset R W
0 0 0 0 0
RW RW RW RW RW
5 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are "0." 7
0
R--
Address 00D716
I2C Data Shift Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C data shift register (S0) [Address 00D716] B 0 to 7 Name Functions After reset Indeterminate RW RW
D0 to D7 This is an 8-bit shift register to store receive data and write transmit data.
Note: To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more.
Address 00D816
I2C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C address register (S0D) [Address 00D816] B
0
Name
Read/write bit (RBW)
Functions
The last significant bit of address data is compared. 0: Wait the first byte of slave address after START condition (read state) 1: Wait the first byte of slave address after RESTART condition (write state) The address data is compared.
After reset R W
0
R--
1 to 7
Slave address (SAD0 to SAD6)
0
RW
Rev. 1.0
105
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Address 00D916
I2C Status Register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register (S1) [Address 00D916] B
0 1 2 3 4 5
Name
Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB)
Functions
0 : Last bit = "0 " 1 : Last bit = "1 " (See note)
After reset R W
Indeterminate 0 0
R-- R-- R-- R-- RW RW RW
0 : No general call detected 1 : General call detected (See note) 0 : Address mismatch 1 : Address match 0 : Not detected 1 : Detected (See note)
0 1 0 0
(See note) 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode
6, 7 Communication mode specification bits (TRX, MST)
Note : These bits and flags can be read out, but cannnot be written.
Address 00DA16
I2C Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D) [Address 00DA16]
B
0 to 2
Name
Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions
b0 0: 8 1: 7 0: 6 1: 5 0: 4 1: 3 0: 2 1: 1
After reset R W
0
RW
3 4 5
I2C-BUS interface use enable bit (ESO) Data format selection bit(ALS) Addressing format selection bit (10BIT SAD)
0: Disabled 1: Enabled 0: Addressing format 1: Free data format 0: 7-bit addressing format 1: 10-bit addressing format b7 b6 Connection port (See note) 0 0: None 0 1: SCL1, SDA1 1 0: SCL2, SDA2 1 1: SCL1, SDA1, SCL2, SDA2
0 0 0 0
RW RW RW RW
6, 7 Connection control bits between I2C-BUS interface and ports (BSEL0, BSEL1)
Rev. 1.0
106
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Address 00DB16
I2C Clock Control Register
b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2) [Address 00DB16]
B
0 to 4
Name
Functions
After reset R W
0
SCL frequency control bits Setup value of Standard clock High speed (CCR0 to CCR4) CCR4-CCR0 mode clock mode 0 0 to 0 2 03 04 05 06 1D 1E 1F Setup disabled Setup disabled Setup disabled Setup disabled 100 83.3 17.2 16.6 16.1 333 250 400 (See note) 166 34.5 33.3 32.3
RW
500/CCR value 1000/CCR value
...
(at = 4 MHz, unit : kHz) 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) 0: Standard clock mode 1: High-speed clock mode 0: ACK is returned. 1: ACK is not returned. 0: No ACK clock 1: ACK clock 0
RW RW RW
6 7
0 0
Note: At 400 kHz in the high-speed clock mode, the duty is as below . "0" period : "1" period = 3 : 2 In the other cases, the duty is as below. "0" period : "1" period = 1 : 1
Address 00DC16
Serial I/O Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 0 Serial I/O mode register (SM) [Address 00DC16] B Name
b1 b0
Functions 0 0: f(XIN)/4 0 1: f(XIN)/16 1 0: f(XIN)/32 1 1: f(XIN)/64 0: External clock 1: Internal clock 0: P40, P41 1: SOUT(/IN), SCLK
0, 1 Internal synchronous clock selection bits (SM0, SM1)
After reset R W 0 RW
2 3
Synchronous clock selection bit (SM2) Serial I/O port selection bit (SM3)
0 0
RW RW
4 Fix this bit to "0." 5 6 7 Transfer direction selection bit (SM5) Serial input pin selection bit (SM6) 0: LSB first 1: MSB first 0: Input signal from SIN pin. 1: Input signal from SOUT pin.
0 0 0 0
RW RW RW R--
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
Rev. 1.0
107
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Address 00E016
Horizontal Position Register
b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HR) [Address 00E0 16]
B 0 to 5
Name
Horizontal display start positions (HR0 to HR5)
Functions
64 steps (0016 to 3F16)
After reset
0 0
RW
RW R--
6, 7 Nothing is assigned. These bits are write disable bits. When thses bits are read out, the values are "0."
Addresses 00E116 and 00E216
Vertical Position Register i
b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register i (CVi) (i = 1 and 2) [Addresses 00E1 16, 00E216]
B 0 to 6 7
Name Vertical display start positions (CVi : CVi0 to CVi6)
Functions 128 steps (0016 to 7F16)
After reset
RW
Indeterminate R W
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
0
R--
Address 00E416
Character Size Register
b7 b6 b5 b4 b3 b2 b1 b0 Character size register (CS) [Address 00E4 16]
B
Name
Functions 00 : Minimum size 01 : Medium size 10 : Large size 11 : Do not set. 00 : Minimum size 01 : Medium size 10 : Large size 11 : Do not set.
After reset
RW
0, 1 Character size of block 1 selection bits (CS10, CS11) 2,3 Character size of block 2 selection bits (CS20,CS21) 4 to 7
Indeterminate R W
Indeterminate R W
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
0
R--
Rev. 1.0
108
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Address 00E516
Border Selection Register
b7 b6 b5 b4 b3 b2 b1 b0 Border selection register (MD) [Address 00E5 16]
B 0 1 2 3 to 7
Name
Functions
After reset R W
Indeterminate R W
Block 1 OUT1 output 0 : Same output as R, G, B is output border selection bit (MD10) 1 : Border output Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0."
0
R--
Block 2 OUT1 output 0 : Same output as R, G, B is output Indeterminate R W border selection bit (MD20) 1 : Border output Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 0 R--
Addresses 00E616 to 00E916
Color Register i
b7 b6 b5 b4 b3 b2 b1 b0 Color regist er i (COi) (i = 0 to 3) [Addresses 00E616 to 00E916]
B 0 1 2 3 4 5 6 7
Name
@
Functions
After reset R W 0 R--
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." B signal output selection bit (COi1) G signal output selection bit (COi2) R signal output selection bit (COi3) 0: No character is output 1: Character is output 0: No character is output 1: Character is output 0: No character is output 1: Character is output
Indeterminate R W
Indeterminate R W
Indeterminate R W
B signal output (background) 0: No background color is output Indeterminate R W selection bit (COi4) (See note 1) 1: Background color is output OUT1 signal output control bit (COi5) (See notes 1, 2) 0: Character is output 1: Blank is output
Indeterminate R W
0: No background color is output Indeterminate R W G signal output (background) selection bit (COi6) (See note 1) 1: Background color is output R signal output (background) 0: No background color is output Indeterminate R W selection bit (COi7) (See note 2) 1: Background color is output
Notes 1: When bit 5 ="0" and bit 4 = "1," there is output same as a character or border output from pin OUT1. Do not set bit 5 = "0" and bit 4 = "0." 2: When only bit 7 ="1" and bit 5 "0," there is output from pin OUT2.
Rev. 1.0
109
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Address 00EA16
CRT Control Register
b7 b6 b5 b4 b3 b2 b1 b0 CRT control register (CC) [Address 00EA16]
B 0 1 2 3 to 6 7
Name All-blocks display control bit (CC0) (See note) Block 1 display control bit (CC1) Block 2 display control bit (CC2)
Functions 0 : All-blocks display off 1 : All-blocks display on 0 : Block 1 display off 1 : Block 1 display on 0 : Block 2 display off 1 : Block 2 display on
After reset R W 0 0 0 0 RW RW RW R--
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." P10/OUT2 pin switch bit (CC7) 0 : P10 1 : OUT2
0
RW
Note: Display is controlled by logical product (AND) between the all-blocks display control bit and each block control bit.
Addresses 00EC16
CRT Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0 CRT port control register (CRTP) [Address 00EC16]
B 0 1 2 3 4 5 6 7
Name HSYNC input polarity switch bit (HSYC) VSYNC input polarity switch bit (VSYC)
Functions 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input
After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW
R/G/B output polarity switch 0 : Positive polarity output 1 : Negative polarity output bit (R/G/B) OUT2 output polarity switch bit (OUT2) OUT1 output polarity switch bit (OUT1) R signal output switch bit (OP5) G signal output switch bit(OP6) B signal output switch bit(OP7) 0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0 : R signal output 1 : MUT E signal output 0 : G signal output 1 : MUT E signal output 0 : B signal output 1 : MUT E signal output
Rev. 1.0
110
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Address 00ED16
CRT Clock Selection Register
b7 b6 b5 b4 b3 b2 b1 b0
000000
CRT clock selection register (CK) [Address 00ED16]
B
Name
Functions
After reset R W 0 RW
0, 1 CRT clock Functions b1 b0 selection bits 0 0 The clock for display is supplied by connecting RC (CK0,CK1) or LC across the pins OSC1 and OSC2. 0 1 Since the main clock is used as the OSD oscillation clock for display, the oscillation frequency frequency is limited. Because of this, = f(XIN) the character size in width (horizontal) 0 OSD oscillation direction is also limited. In this case, frequency pins OSC1 and OSC2 are also used = f(XIN)/1.5 as input ports P36 and P37 respectively. 1 The clock for OSD is supplied by connecting the following across the pins OSC1 and OSC2. * a ceramic resonator only for OSD and a feedback resistor * a quartz-crystal oscillator only for OSD and a feedback resistor (See note)
1
1
2 to 7 Fix these bits to "0."
0
RW
Note: It is necessary to connect other ceramic resonator or quartz-crystal oscillator across the pins XN and XOUT. I
Addresses 00EE16
A-D Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
A-D mode register (ADM) [Address 00EE16]
B
0 to 2
Name
Analog input pin selection bits (ADM0 to ADM2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1
Functions
b0 0 : A-D1 1 : A-D2 0 : A-D3 1 : A-D4 0 : A-D5 1 : A-D6 0 : A-D7 1 : A-D8
After reset R W
0
RW
3 4 5 to 7
This bit is a write disable bit. When this bit is read out, the value is "0." Storage bit of comparison result (ADM4) 0: Input voltage < reference voltage 1: Input voltage > reference voltage
0 Indeterminate 0
R-- R-- R--
Nothing is assigned. This bits are write disable bits. When these bits are read out, the values are "0."
Rev. 1.0
111
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Address 00EF16
A-D Control Register
b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (ADC) [Address 00EF16]
B 0 to 5
Name D-A converter set bits (ADC0 to ADC5) b5 0 0 0 b4 0 0 0 b3 0 0 0
Functions b2 0 0 0 b1 0 0 1 b0 0 : 1/128Vcc 1 : 3/128Vcc 0 : 5/128Vcc
After reset 0
RW RW
1 1 1
1 1 1
1 1 1
1 1 1
0 1 1
1 : 123/128Vcc 0 : 125/128Vcc 1 : 127/128Vcc 0 R--
6, 7 Nothing is assigned. These bits are write disable bits. When these bits are reed out, the values are " 0."
Addresses 00F416
Timer 12 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 0 Timer mode register (T12M) [Address 00F416] B 0 1 Name Functions After reset R W 0 0 0 0 0 RW RW RW RW RW
Timer 1 count source 0: f(XIN)/16 selection bit 1 (T12M0) 1: f(XIN)/4096 Timer 2 count source selection bit (T12M1) 0: Interrupt clock source 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 1: Timer 1 overflow
2 Timer 1 count stop bit (T12M2) 3 Timer 2 count stop bit (T12M3) 4 Timer 2 internal count source selection bit 2 (T12M4) 5 Fix this bit to "0."
0 0
RW R--
6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
Rev. 1.0
112
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Address 00F516
Timer 34 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 34 mode register (T34M) [Address 00F516] B Name 0 Timer 3 count source selection bit (T34M0) 1 Timer 4 internal interrupt count source selection bit (T34M1) Functions 0 : f(XIN)/16 1 : External clock source 0 : Timer 3 overflow signal 1 : f(XIN)/16 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Internal clock source 1: f(XIN)/2 After reset R W 0 RW 0 RW
2 Timer 3 count stop bit (T34M2) 3 Timer 4 count stop bit (T34M3) 4 Timer 4 count source selection bit (T34M4) 5
0 0 0 0
RW RW RW RW
Timer 3 external count 0: TIM3 pin input source selection bit 1: HSYNC pin input (T34M5)
6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
0
R--
Addresses 00F916
Interrupt Input Polarity Register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Interrupt input polarity register(RE) [Address 00F916]
B
Name
Functions
After reset 0 0
RW R-- RW RW RW RW R-- RW
0, 1 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 2 3 4 5 6 7 Fix this bit to "0." INT1 polarity switch bit (RE3) INT2 polarity switch bit ( E 4) R INT3 polarity switch bit ( E 5) R 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity
0 0 0 0 0
Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." Fix this bit to "0."
Rev. 1.0
113
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Address 00FB16
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0 11111 00 CPU mode register (CM) [Address 00FB16] B Name Functions
After reset R W
Indeterminate
0, 1 Fix these bits to "0." 2 Stack page selection bit (CM2) (See note) 0: 0 page 1: 1 page
RW RW RW
1
Indeterminate
3 to 7 Fix these bits to "1." Note: This bit is set to "1" after the reset release.
Addresses 00FC16
Interrupt Request Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC16] B Name 0 Timer 1 interrupt request bit (TM1R) 1 2 3 4 5 6 7 Functions After reset 0 0 : No interrupt request issued 1 : Interrupt request issued Timer 2 interrupt 0 0 : No interrupt request issued request bit (TM2R) 1 : Interrupt request issued 0 Timer 3 interrupt 0 : No interrupt request issued request bit (TM3R) 1 : Interrupt request issued 0 Timer 4 interrupt 0 : No interrupt request issued request bit (TM4R) 1 : Interrupt request issued OSD interrupt request 0 : No interrupt request issued 0 1 : Interrupt request issued bit (OSDR) VSYNC interrupt 0 0 : No interrupt request issued request bit (VSCR) 1 : Interrupt request issued 0 Multi-master I2C-BUS interface 0 : No interrupt request issued interrupt request bit (IICR) 1 : Interrupt request issued 0 0 : No interrupt request issued INT3 external interrupt request bit (IT3R) 1 : Interrupt request issued RW RV RV RV RV RV RV RV RV
V: "0" can be set by software, but "1" cannot be set.
Rev. 1.0
114
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Address 00FD16
Interrupt Request Register 2
b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD16] B Name 0 INT1 external interrupt
request bit (IT1R)
Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued
After reset R W 0 0 0 0 0 0 0 RV RV RV R-- RV R-- RW
1 2
INT2 external interrupt request bit (IT2R)
0 : No interrupt request issued 1 : Interrupt request issued 3 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." 4 f(XIN)/4096 interrupt 0 : No interrupt request issued request bit (MSR) 1 : Interrupt request issued 5, 6 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 7 Fix this bit to "0." V: "0" can be set by software, but "1" cannot be set.
Serial I/O interrupt request bit (S1R)
Addresses 00FE16
Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW
0 Timer 1 interrupt enable bit (TM1E) 1 Timer 2 interrupt enable bit (TM2E) 2 Timer 3 interrupt enable bit (TM3E) 3 Timer 4 interrupt enable bit (TM4E) 4 OSD interrupt enable bit (OSDE) 5 VSYNC interrupt enable bit (VSCE)
6 Multi-master I2C-BUS interface 0 : Interrupt disabled interrupt enable bit (IICE) 1 : Interrupt enabled 7 INT3 external interrupt enable bit (IT3E) 0 : Interrupt disabled 1 : Interrupt enabled
Rev. 1.0
115
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Address 00FF16
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0 00 0 Interrupt control register 2 (ICON2) [Address 00FF16] B Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset 0 0 0 0 0 : Interrupt disabled 1 : Interrupt enabled 0 0
indeterminate
RW RW RW RW RW RW RW R-
0 INT1 external interrupt enable bit (IT1E) 1 INT2 external interrupt enable bit (IT2E) 2 Serial I/O interrupt enable bit (S1E) 3 Fix this bit to "0." 4 f(XIN)/4096 interrupt enable bit (MSE) 5, 6 Fix these bits to "0." 7
Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "indeterminate."
Addresses 021B16
ROM Correction Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
00
ROM correction enable register (RCR) [Address 021B16] B
0 1
Name
Vector 1 enable bit (RC0) Vector 2 enable bit (RC1)
Functions
0: Disabled 1: Enabled 0: Disabled 1: Enabled
After reset R W
0 0 0 0
RW RW RW R--
2, 3 Fix these bits to "0." 4 to 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0."
Rev. 1.0
116
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
21. PACKAGE OUTLINE
52P4B
EIAJ Package Code SDIP52-P-600-1.78 JEDEC Code - Weight(g) 5.1 Lead Material Alloy 42/Cu Alloy
Plastic 52pin 600mil SDIP
52
27
1
26
Symbol
D
e SEATING PLANE
b1
b
b2
A A1 A2 b b1 b2 c D E e e1 L
Dimension in Millimeters Min Nom Max - - 5.5 0.51 - - - 3.8 - 0.4 0.5 0.6 0.9 1.0 1.3 0.65 0.75 1.05 0.22 0.27 0.34 45.65 45.85 46.05 12.85 13.0 13.15 - 1.778 - - 15.24 - 3.0 - - 0 - 15
A
80P6N-A
EIAJ Package Code QFP80-P-1420-0.80 HD D JEDEC Code - Weight(g) 1.58 Lead Material Alloy 42
A1
L
A2
Plastic 80pin 14!20mm body QFP
MD
1
64
b2
I2 Recommended Mount Pad
HE
Symbol A A1 A2 b c D E e HD HE L L1 y b2 I2 MD ME
24
41
25
40
A L1
A1
e y
b
F
L
Detail F
Dimension in Millimeters Min Nom Max 3.05 - - 0.1 0.2 0 2.8 - - 0.3 0.35 0.45 0.13 0.15 0.2 13.8 14.0 14.2 19.8 20.0 20.2 0.8 - - 16.5 16.8 17.1 22.5 22.8 23.1 0.4 0.6 0.8 1.4 - - 0.1 - - 0 10 - 0.5 - - - - 1.3 14.6 - - 20.6 - -
E
A2
Rev. 1.0
117
c
ME
80
65
e
e1
E
c
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
Keep safety first in your circuit designs!
* Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
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(c) 1999 MITSUBISHI ELECTRIC CORP. New publication, effective Sep. 1999. Specifications subject to change without notice.
MITSUBISHI MICROCOMPUTERS
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP M37212EFSP/FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER
REVISION HISTORY
Rev. No. 1.0 PDF First Edition
M37212M4/M8-XXXSP, M37212M6-XXXSP/FP, M37212EFSP/FP (Rev.1.0) DATA SHEET
Revision Description Rev. date 9909
Rev. 1.0
(1/1)
119

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